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61.发明申请公开(公告)号：US20090037864A1
公开(公告)日：2009-02-05
申请号：US12013356
申请日：2008-01-11
IPC分类号： G06F9/455
CPC分类号： H01L27/11807 , G06F17/5068 , G06F2217/12 , H01L23/5226 , H01L23/528 , H01L27/0207 , H01L27/11803 , H01L2027/1182 , H01L2027/11866 , H01L2027/11874 , H01L2027/11888 , Y02P90/265
摘要： A method is provided for designing a semiconductor chip having one or more functionally interfaced dynamic array sections. A virtual grate is laid out for conductive features used to define a gate electrode level of a dynamic array section. The virtual grate is defined by a framework of parallel lines defined at a substantially constant pitch. One or more conductive features are arranged along every line of the virtual grate. For each line of the virtual grate, a gap is defined between proximate ends of each pair of adjacent conductive features which are arranged along a common line of the virtual grate. Each gap is defined to maintain a substantially consistent separation between proximate ends of conductive features. Each conductive feature is defined to be devoid of a substantial change in direction, such that the conductive features remain substantially aligned to the framework of parallel lines of the virtual grate.
摘要翻译： 提供了一种用于设计具有一个或多个功能接口的动态阵列部分的半导体芯片的方法。 布置了用于定义动态阵列部分的栅电极电平的导电特征的虚拟格栅。 虚拟炉排由以基本上恒定的间距定义的平行线的框架限定。 一个或多个导电特征沿着虚拟格栅的每一行布置。 对于虚拟格栅的每一行，在沿着虚拟格栅的公共线布置的每对相邻导电特征的近端之间限定间隙。 每个间隙被限定为保持导电特征的近端之间的基本一致的间隔。 每个导电特征被定义为没有方向的实质变化，使得导电特征保持基本上与虚拟格栅的平行线的框架对准。
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公开(公告)号：US20090014811A1
公开(公告)日：2009-01-15
申请号：US12212562
申请日：2008-09-17
IPC分类号： H01L27/105
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate portion and a number of diffusion regions defined within the substrate portion. The diffusion regions are separated from each other by a non-active region of the substrate portion. The semiconductor device includes a number of linear gate electrode segments defined to extend over the substrate portion in a single common direction. In one embodiment, the diffusion regions are defined in a non-symmetrical manner relative to a centerline of the substrate portion. In another embodiment, the substrate portion corresponds to a region of the semiconductor device in which first and second cells are defined, and respectively include diffusion shapes of different size. In another embodiment, one or more of the diffusion regions is defined to have a periphery formed by more than four orthogonally related sides.
摘要翻译： 半导体器件包括衬底部分和限定在衬底部分内的多个扩散区域。 扩散区域通过衬底部分的非有源区域彼此分离。 半导体器件包括多个线性栅极电极段，其被限定为在单个共同方向上在衬底部分上延伸。 在一个实施例中，扩散区域相对于衬底部分的中心线以非对称的方式限定。 在另一个实施例中，衬底部分对应于其中限定了第一和第二单元的半导体器件的区域，并且分别包括不同尺寸的扩散形状。 在另一个实施例中，一个或多个扩散区域被限定为具有由多于四个正交相关侧面形成的周边。
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公开(公告)号：US20080222587A1
公开(公告)日：2008-09-11
申请号：US12041584
申请日：2008-03-03
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G03F1/70 , G06F17/5068 , G06F17/5072 , G06F17/5077 , G06F2217/12 , H01L27/11807
摘要： A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.
摘要翻译： 公开了一种用于定义集成电路设计中使用的多重图案化电池布局的方法。 根据动态阵列架构为单元格的级别定义布局，以便包括多个布局特征。 布局特征的数量是线性的并且通常定向。 布局被拆分为单元格级别的多个子布局。 布局中的布局特征中的每一个都被分配给任何一个子布局。 此外，布局被拆分，使得每个子布局是独立可编制的。 单元级别的子布局存储在计算机可读介质上。
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公开(公告)号：US10651200B2
公开(公告)日：2020-05-12
申请号：US13831605
申请日：2013-03-15
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/088 , H01L27/118 , H01L27/11 , G11C11/412 , G11C5/06 , H01L27/02 , H01L27/092 , G06F17/50 , H01L23/538 , H01L23/498 , H01L21/8234 , H01L23/528 , H01L27/105
摘要： A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.
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公开(公告)号：US10186523B2
公开(公告)日：2019-01-22
申请号：US16119794
申请日：2018-08-31
IPC分类号： H01L27/10 , H01L27/118 , G06F17/50 , H01L27/092 , H01L21/28 , H01L29/423 , H01L21/8238 , H01L27/088 , H01L27/02 , H01L23/528 , H01L23/522
摘要： An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.
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66.发明授权公开(公告)号：US10141334B2
公开(公告)日：2018-11-27
申请号：US15688187
申请日：2017-08-28
IPC分类号： H01L27/118 , H01L27/092 , H01L23/522 , G06F17/50 , H01L21/28 , H01L29/423 , H01L23/528 , H01L21/8238 , H01L27/088 , H01L27/02
摘要： Gate structures are positioned within a region in accordance with a gate horizontal grid that includes at least seven gate gridlines separated from each other by a gate pitch of less than or equal to about 193 nanometers. Each gate structure has a substantially rectangular shape with a width of less than or equal to about 45 nanometers and is positioned to extend lengthwise along a corresponding gate gridline. Each gate gridline has at least one gate structure positioned thereon. A first-metal layer is formed above top surfaces of the gate structures within the region and includes first-metal structures positioned in accordance with a first-metal vertical grid that includes at least eight first-metal gridlines. Each first-metal structure has a substantially rectangular shape and is positioned to extend along a corresponding first-metal gridline. At least six contact structures of substantially rectangular shape contact the at least six gate structures.
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公开(公告)号：US10020321B2
公开(公告)日：2018-07-10
申请号：US13831530
申请日：2013-03-14
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/11 , H01L27/092 , H01L27/118 , G11C11/412 , G11C5/06 , H01L27/02 , G06F17/50 , H01L27/088 , H01L23/538 , H01L23/498 , H01L21/8234 , H01L23/528 , H01L27/105
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a second gate electrode track. A second PMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along the first gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.
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68.发明授权公开(公告)号：US09910950B2
公开(公告)日：2018-03-06
申请号：US15243748
申请日：2016-08-22
IPC分类号： G06F17/50 , H01L27/02 , H01L27/118 , H01L23/48
CPC分类号： G06F17/5072 , G06F17/5054 , G06F17/5068 , G06F2217/12 , H01L23/48 , H01L27/0207 , H01L27/11803 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell.
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公开(公告)号：US09673825B2
公开(公告)日：2017-06-06
申请号：US14181556
申请日：2014-02-14
发明人： Scott T. Becker
CPC分类号： H03K19/20 , G06F17/5068 , H03K19/215
摘要： An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.
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公开(公告)号：US09633987B2
公开(公告)日：2017-04-25
申请号：US14195600
申请日：2014-03-03
IPC分类号： G06F17/50 , H01L27/00 , H01L27/02 , G03F1/70 , H01L27/118
CPC分类号： H01L27/0207 , G03F1/70 , G06F17/5068 , G06F17/5072 , G06F17/5077 , G06F2217/12 , H01L27/11807
摘要： A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.
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