公开(公告)号：US09714978B2

公开(公告)日：2017-07-25

申请号：US13862244

申请日：2013-04-12

申请人： Larry Ross ,  Michael Bruce

发明人： Larry Ross ,  Michael Bruce

IPC分类号： G01R31/3177 ,  G01R31/28 ,  G01R31/311

CPC分类号： G01R31/2882 ,  G01R31/311

摘要： A method, system, and computer program product for integrated circuit wafer and die testing. The method commences by selecting areas of interest accessible from a backside of an integrated circuit where the areas of interest correspond to electronic devices (e.g., gates or transistors or vias or pads). Then, using a small-beam light source such as a laser, illuminating the areas of interest and collecting the reflected signal returned from illuminated areas of interest. A processor analyses the reflected signal to determine logic states and timing information of the electronic devices and compares the determined logic states and timing information to a pre-determined logic pattern to identify one or more errors as observed from the actual electronic devices. Specific points within an area of interest are determined from CAD layout data, and the pre-determined logic patterns can be retrieved from CAD simulation data.

公开(公告)号：US09684035B1

公开(公告)日：2017-06-20

申请号：US15285114

申请日：2016-10-04

申请人： International Business Machines Corporation

发明人： Chandrasekharan Kothandaraman

IPC分类号： G01R27/28 ,  G01R31/327 ,  H03K3/03 ,  G11C29/08 ,  G01R31/28 ,  G11C11/16

CPC分类号： G01R31/3277 ,  G01R31/2882 ,  G01R31/3278 ,  G11C11/16 ,  G11C29/08 ,  H03K3/0315 ,  H03K3/59

摘要： Circuits are provided for modeling and characterizing the switching of magnetic tunnel junctions (MTJ) elements. More specifically, ring oscillators loaded with MTJ elements are used to characterize magnetic tunnel junction (MTJ) element performance. The circuits can include a ring oscillator (RO) having an odd number of inverters connected in series with a magnetic tunnel junction (MTJ) element inserted between each inverter. In some embodiments, the magnetic tunnel junction (MTJ) elements are arranged to act as a load to the inverters. The circuits optionally include one or more of a time to amplitude converter, a pulse distribution analyzer and/or PFET(s) and NFET(s). Methods of characterizing the switching characteristics of MTJ elements are also provided herein. Such MTJ elements can be suitable for use in magnetoresistive random access memory (MRAM) devices. Methods of making the ring oscillator are further provided herein.

公开(公告)号：US20170160339A1

公开(公告)日：2017-06-08

申请号：US14962043

申请日：2015-12-08

申请人： International Business Machines Corporation

发明人： Keith A. Jenkins

IPC分类号： G01R31/28

CPC分类号： G01R31/2882

摘要： A computer system may determine a first set of output values for a set of test paths at a first time. Each output value may correspond to a test path in the set of test paths. The computer system may then determine a second set of output values at a second time. Each output value in the second set of output values may have an associated output value in the first set of output values. The computer system may then determine whether degradation of the semiconductor chip has occurred by comparing the first set of output values to the second set of output values.

公开(公告)号：US09599670B2

公开(公告)日：2017-03-21

申请号：US14030684

申请日：2013-09-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Sandeep Kumar Goel

IPC分类号： G01R31/3185 ,  G01R31/28 ,  G01R31/317

CPC分类号： G01R31/318513 ,  G01R31/2882 ,  G01R31/31707 ,  G01R31/31718

摘要： A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) path delay test circuit and at least a portion of a critical path in one of its layers. The test circuit includes a plurality of inputs, outputs, a flip-flop coupled to the at least a portion of the critical path and a multiplexer coupled to the flip-flop and to a second layer of the IC. The test circuit further includes a control element such that path delay testing of the IC may be conducted on a layer-by-layer basis.

公开(公告)号：US09568548B1

公开(公告)日：2017-02-14

申请号：US14882668

申请日：2015-10-14

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Robert L. Franch ,  Phillip J. Restle ,  David Wen-Hao Shan

IPC分类号： G01R31/317 ,  G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/2882 ,  G01R31/31922

摘要： A delay measurement technique using a tapped delay line edge capture circuit that captures tap position of edges within the delay line provides accuracy of measurement to one pico-second and below. A control circuit causes latches to capture an edge of a signal delayed through the delay line at taps of the delay line. The frequency of a clock from which the signal is derived is adjusted and tap outputs are captured by latches and averaged. A first frequency is found at which the average edge position is midway between two adjacent tap positions. A second signal, which may be the reference signal that clocks the latches, is propagated through the delay line and a second frequency is found for which the average edge position lies at the boundary between the two tap positions. The delay is determined from the difference between the periods of the first frequency and the second frequency.

摘要翻译： 使用捕获的延迟线边缘捕获电路的延迟测量技术捕获延迟线内的边缘的抽头位置，将测量精度提高到一个微秒以下。 控制电路使得锁存器捕获在延迟线的抽头处延迟通过延迟线的信号的边沿。 调整信号导出的时钟频率，并通过锁存器捕获抽头输出并进行平均。 找到第一频率，平均边缘位置在两个相邻的抽头位置之间的中间。 第二信号（其可以是对锁存器进行时钟的参考信号）通过延迟线传播，并且找到第二频率，平均边缘位置位于两个分接位置之间的边界处。 延迟由第一频率和第二频率的周期之间的差确定。

公开(公告)号：US20160211836A1

公开(公告)日：2016-07-21

申请号：US14913309

申请日：2014-07-29

申请人： JAPAN SCIENCE AND TECHNOLOGY AGENCY

发明人： Hidetoshi ONODERA ,  Islam A.K.M MAHFUZUL

IPC分类号： H03K5/134 ,  G01R31/28

CPC分类号： H03K5/134 ,  G01R31/2882 ,  H03K2005/00019

摘要： A delay circuit contains a first inversion circuit including a pull-up circuit and a pull-down circuit, and a second inversion circuit including a pull-up circuit and a pull-down circuit. The delay circuit further contains a first pass transistor connected in series to the pull-up circuit in the first inversion circuit between a power supply potential and an output node, a second pass transistor connected in series to the pull-down circuit in the first inversion circuit between a ground potential and the output node, a third pass transistor connected in series between the input node and the pull-up circuit in the second inversion circuit, and a fourth pass transistor connected in series between the input node and the pull-down circuit in the second inversion circuit. A delay characteristic of the delay circuit is changed by a combination of control signals applied to gates of the pass transistors.

摘要翻译： 延迟电路包括包括上拉电路和下拉电路的第一反相电路，以及包括上拉电路和下拉电路的第二反相电路。 延迟电路还包括与电源电位和输出节点之间的第一反相电路中的上拉电路串联连接的第一级晶体管，在第一反相中串联连接到下拉电路的第二级晶体管 接地电位和输出节点之间的电路，串联连接在第二反相电路中的输入节点和上拉电路之间的第三传输晶体管，以及串联连接在输入节点和下拉电路之间的第四传输晶体管 电路在第二反向电路中。 通过施加到通过晶体管的栅极的控制信号的组合来改变延迟电路的延迟特性。

公开(公告)号：US20160169961A1

公开(公告)日：2016-06-16

申请号：US14831807

申请日：2015-08-20

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： STEVE L. LECLERC

IPC分类号： G01R31/28

CPC分类号： G01R31/31724 ,  G01R31/2803 ,  G01R31/2834 ,  G01R31/2851 ,  G01R31/2856 ,  G01R31/2882 ,  G01R31/303 ,  G01R31/31701 ,  G01R31/31712 ,  G01R31/31718 ,  G01R31/318597 ,  G01R31/31907 ,  G01R31/31908

摘要： A test controller controlled by a design entity sends at least one closed type command of a closed loop architecture test flow to an arbiter of a vendor test platform controlled by a vendor entity, wherein the test controller controls nondeterministic testing on a protected integrated circuit (IC) integrated into an electronic assembly, as performed by test equipment hardware within the vendor test platform, without the design entity disclosing an underlying design of the protected IC to the vendor entity. In response to the test controller receiving at least one response of the at least one closed type command, from the arbiter interface passing the at least one closed type command directly through the test equipment hardware to the protected IC, determining, by the test controller, based on the at least one response, a next at least one closed type command of the closed loop architecture test flow to send to the arbiter.

公开(公告)号：US09229054B2

公开(公告)日：2016-01-05

申请号：US13976931

申请日：2011-09-28

申请人： Keith A. Bowman ,  Carlos Tokunaga ,  James W. Tschanz

发明人： Keith A. Bowman ,  Carlos Tokunaga ,  James W. Tschanz

IPC分类号： G01R31/3187 ,  G01R31/317 ,  G01R31/3193 ,  G01R31/26 ,  G01R31/28 ,  G06F1/10

CPC分类号： G01R31/31707 ,  G01R31/2642 ,  G01R31/2882 ,  G01R31/31725 ,  G01R31/31937 ,  G06F1/10

摘要： An aging monitor circuit that provides a more accurate estimate of aging and/or delay in a circuit and/or circuit path. The aging monitor circuit employs a separate aging path with driving and receiving flip flops (FFs) and a tunable replica circuit (TRC) to enable measurements of single-transition DC-stressed path delay that only propagates through stressed transistors or other circuit element(s). A finite state machine (FSM) in the aging monitor circuit is configured to adjust a frequency of a clock signal output by a digitally controlled oscillator (DCO) in response to an error signal output by the receiving FF. The error signal is generated in response to single-transition DC-stressed path delay; and therefore enables the adjustment of the frequency of the dock signal to correspond to an amount or effect of the delay.

摘要翻译： 一种老化监视电路，可以更准确地估计电路和/或电路路径中的老化和/或延迟。 老化监测电路采用单独的老化路径，具有驱动和接收触发器（FF）和可调谐复制电路（TRC），以便能够测量仅通过应力晶体管或其他电路元件传播的单跃迁DC应力路径延迟 ）。 老化监视电路中的有限状态机（FSM）被配置为响应于由接收FF输出的误差信号来调节由数字控制振荡器（DCO）输出的时钟信号的频率。 误差信号是响应单跃变直流应力路径延迟而产生的; 因此能够调整对接信号的频率以对应于延迟的量或效果。

公开(公告)号：US09213054B2

公开(公告)日：2015-12-15

申请号：US13985364

申请日：2012-03-14

申请人： Frederick A. Ware

发明人： Frederick A. Ware

IPC分类号： G01R31/26 ,  G01R31/317 ,  G11C29/02 ,  G11C29/12 ,  G11C29/16 ,  G11C29/50 ,  H03L7/00 ,  G11C29/04

CPC分类号： G01R31/2882 ,  G01R31/2607 ,  G01R31/31726 ,  G11C29/022 ,  G11C29/12015 ,  G11C29/16 ,  G11C29/50012 ,  G11C2029/0401 ,  H03L7/00

摘要： A semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The semiconductor IC device further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

摘要翻译： 半导体IC器件包括用于传送定时信号的定时电路，所述定时电路被配置为接收第一测试信号并且响应于所述第一测试信号而在定时信号中产生延迟，所述第一测试信号包括第一定时 事件。 所述半导体IC器件还包括接口电路，其被配置为响应于所述定时信号传送所述数据信号，所述接口电路还被配置为接收第二测试信号并响应于所述第二测试信号而实现所述数据信号的延迟 所述第二测试信号包括根据测试标准与所述第一定时事件相关的第二定时事件。

公开(公告)号：US20150309111A1

公开(公告)日：2015-10-29

申请号：US14262778

申请日：2014-04-27

申请人： Texas Instruments Incorporated

发明人： Soy Ying Seah ,  Gunvant Patel

IPC分类号： G01R31/28

CPC分类号： G01R31/2882 ,  G01R31/2894 ,  G01R31/31718 ,  G01R31/31919

摘要： Screening a batch of integrated circuits (IC) may be done with test patterns provided in a sequence of test vectors. The sequence of test vectors may be fetched from a memory coupled to a tester and then one or more bits from each test vector may be provided to the tester. A test pattern is formed by updating a latch in a periodic manner with a bit value from a same bit position from each of the sequence of test vectors. The test pattern may then be applied to an input pin of a device under test and a resulting signal may be monitored on an output pin of each one of the batch of ICs. A slow speed ICs may be screened by treating each IC that passes both a fast pattern test and a slow speed pattern test as a failure, for example.

摘要翻译： 可以使用在一系列测试向量中提供的测试模式来筛选一批集成电路（IC）。 测试向量的序列可以从耦合到测试器的存储器中取出，然后可以向测试器提供来自每个测试向量的一个或多个比特。 通过用来自每个测试向量序列的相同比特位置的位值以周期方式更新锁存器来形成测试模式。 然后可以将测试图案应用于被测设备的输入引脚，并且可以在该批IC中的每一个的输出引脚上监视所得到的信号。 例如，可以通过将通过快速模式测试和慢速模式测试的每个IC作为故障来屏蔽慢速IC。