公开(公告)号：US06320431B1

公开(公告)日：2001-11-20

申请号：US09430849

申请日：1999-11-01

Applicant: David Potson ,  Mark F. Rives

Inventor： David Potson ,  Mark F. Rives

IPC: H03B2100

CPC classification number: G06F1/0353 ,  G06F1/0328 ,  G06F1/0342 ,  G06F2211/902

Abstract: An apparatus according to a preferred embodiment of the present invention includes two memories each storing different octants of a sine (or cosine) waveform. The sine and cosine waveforms may be concurrently generated by alternately accessing each memory in succession. It is unnecessary to access one memory concurrently, so that both waveforms may be concurrently generated without requiring either two accesses to the same memory or a doubled memory size.

Abstract translation: 根据本发明的优选实施例的装置包括两个存储器，每个存储器具有正弦（或余弦）波形的不同八分圆。 可以通过相继地交替地访问每个存储器来同时产生正弦和余弦波形。 不需要同时访问一个存储器，从而可以同时产生两个波形，而不需要对相同存储器的两次访问或双倍的存储器大小。

公开(公告)号：US20010016863A1

公开(公告)日：2001-08-23

申请号：US09777437

申请日：2001-02-06

Applicant: Anritsu Corporation

Inventor： Masaharu Uchino ,  Kazuhiko Ishibe

IPC: H03B021/00 ,  G06F001/02

CPC classification number: G06F1/0328

Abstract: An amplitude data generator receives L-bit data, and outputs amplitude data of a predetermined periodic function of a phase specified by the data. A frequency setter sets frequency data of (KnullLnull1) bits obtained by dividing a desired output frequency by a frequency of a predetermined clock signal. A K bit counter counts the clock signal. L-set product and sum computation circuits subject the frequency data of (KnullLnull1) bits into L-set K-bit data in which a start bit is shifted by one bit each other. Then, these circuits compute a logical product between the counter output of K bits from the counter and a bit unit, and obtains a total number of bits for each set when the computation result is 1. A shifting/adding circuit adds each total number data obtained by the L-set product and sum computation circuits by shifting a bit, and outputs the least significant L bits of the computation result to the amplitude data generator.

Abstract translation: 振幅数据生成器接收L位数据，并且输出由数据指定的相位的预定周期函数的幅度数据。 频率设定器将通过将期望的输出频率除以预定时钟信号的频率而获得的（K + L-1）比特的频率数据。 K位计数器对时钟信号进行计数。 L组乘积和求和计算电路使（K + L-1）位的频率数据进入L位K位数据，其中起始位相互偏移1位。 然后，这些电路计算来自计数器的K位的计数器输出与位单位之间的逻辑积，并且当计算结果为1时，获得每组的总位数。移位/相加电路将每个总数数据 通过移位一个位由L组积和和计算电路获得，并将计算结果的最低有效L位输出到幅度数据生成器。

公开(公告)号：US06262604B1

公开(公告)日：2001-07-17

申请号：US09339100

申请日：1999-06-24

Applicant: Pascal Gabet ,  Jean-Luc de Gouy

Inventor： Pascal Gabet ,  Jean-Luc de Gouy

IPC: H03B1900

CPC classification number: G06F1/0328

Abstract: A digital frequency synthesizer comprises means for the generation of the samples of a digital signal to be converted into an analog signal encoded on N bits as a function of a frequency control word, means for the generation of a noise signal encoded on N bits, and a digital-analog converter, the useful signal and the noise signal being truncated to M bits before being added up by an adder. The result of the addition is converted into analog signal form by the digital-analog converter. The generated noise has at least a noise density substantially equal to a law of equiprobability, this density being zero outside a given space. Application especially to direct digital synthesis, for example in the field of radar techniques or that of instrumentation.

Abstract translation: 数字频率合成器包括用于产生要转换为以N位编码的模拟信号作为频率控制字的函数的数字信号的采样的装置，用于产生以N位编码的噪声信号的装置，以及 数字模拟转换器，有用信号和噪声信号被加法器相加之前被截断为M位。 加法的结果由数模转换器转换成模拟信号形式。 所产生的噪声至少具有基本上等于等能性定律的噪声密度，该密度在给定空间外为零。 特别适用于直接数字合成，例如在雷达技术领域或仪器领域。

公开(公告)号：US6005419A

公开(公告)日：1999-12-21

申请号：US834360

申请日：1997-04-16

Applicant: Ronald M. Rudish

Inventor： Ronald M. Rudish

IPC: H03B21/00

CPC classification number: G06F1/0328 ,  G06F1/0342

Abstract: A direct digital synthesizer circuit and method for reducing the harmonic content in a synthesized output signal. The direct digital synthesizer generates first and second address signals driving first and second sine look-up read only memory (sine ROM) circuits. The first and second sine ROMs generate first and second digital sine wave signals which are offset in phase from one another by 180 degrees. The first and second digital sine wave signals are converted to first and second analog sine wave signals. The first and second analog sine wave signals are combined in a subtractor circuit. As a result of the phase relationship between the first and second analog sine wave signals, the fundamental component of these signals are emphasized by subtraction while the second harmonic component of theses signals are simultaneously de-emphasized.

Abstract translation: 一种用于减少合成输出信号中的谐波含量的直接数字合成器电路和方法。 直接数字合成器产生驱动第一和第二正弦查找只读存储器（正弦ROM）电路的第一和第二地址信号。 第一和第二正弦ROM产生相位相差180度的第一和第二数字正弦波信号。 第一和第二数字正弦波信号被转换为第一和第二模拟正弦波信号。 第一和第二模拟正弦波信号被组合在减法器电路中。 作为第一和第二模拟正弦波信号之间的相位关系的结果，这些信号的基波分量通过减法被强调，而这些信号的二次谐波分量同时被去强调。

公开(公告)号：US5898325A

公开(公告)日：1999-04-27

申请号：US895717

申请日：1997-07-17

Applicant: David T. Crook ,  Thomas E. Tice ,  James A. Surber, Jr.

Inventor： David T. Crook ,  Thomas E. Tice ,  James A. Surber, Jr.

IPC: H03B21/00 ,  H03L7/18

CPC classification number: H03B21/00 ,  G06F1/0328

Abstract: A dual-tunable direct digital synthesizer is provided with a programmable frequency multiplier that multiplies a relatively low frequency fixed clock signal F.sub.clk so that the output frequency F.sub.o of the waveform is:F.sub.o =(F.sub.n /2.sup.N).times.(M.times.F.sub.clk)where N is the resolution of the digital control word, the tuning word F.sub.n is the value of the N-bit control word, M is the multiplication factor and M*F.sub.clk is the DDS clock frequency. The multiplication factor and, hence, the DDS clock can be reduced to track changes in the output frequency thereby lowering the average power consumption. Because the synthesizer can generate the same output frequency using different tuning word-to-DDS clock ratios, it can be tuned for optimum SFDR over a narrow band around the desired output frequency. In other words, an "enhanced dynamic range band" in the harmonic and spurious performance can be mapped out for each frequency in the bandwidth.

Abstract translation: 双调谐直接数字合成器具有可编程倍频器，其将相对低频的固定时钟信号Fclk相乘，使得波形的输出频率Fo为：Fo =（Fn / 2N）×（MxFclk）其中N为 数字控制字的分辨率，调谐字Fn是N位控制字的值，M是乘法因子，M * Fclk是DDS时钟频率。 因此，可以减少乘法因子和DDS时钟以跟踪输出频率的变化，从而降低平均功耗。 由于合成器可以使用不同的调谐字DDS时钟比产生相同的输出频率，因此可以针对所需输出频率周围的窄带调节最佳SFDR。 换句话说，可以为带宽中的每个频率映射谐波和杂散性能中的“增强型动态范围带”。

公开(公告)号：US5864492A

公开(公告)日：1999-01-26

申请号：US774300

申请日：1996-12-24

Applicant: Philippe Roger Sadot

Inventor： Philippe Roger Sadot

IPC: G06F1/03 ,  H04L27/20 ,  H04L27/36 ,  G06F1/02

CPC classification number: H04L27/365 ,  G06F1/0328 ,  H04L27/2092 ,  G06F2211/902

Abstract: A digital synthesizer for producing a digital frequency signal includes a phase accumulator for repeatedly accumulating a phase value to generate samples of a digital sawtooth signal and a look-up table of digital samples for converting the digital sawtooth signal to a digital waveshape signal. In order to reduce the effect of the quantization of the digital samples, the synthesizer also includes a randomizer for applying a randomizing factor to output digital samples for forming the digital frequency signal. The randomizer includes a randomizing factor generator connected to receive P bits of each digital sample for generating at least one randomizing bit and an summer for summing the remaining N bits of the digital sample and the at least one randomizing bit to generate a digital waveshape sample of the digital frequency signal.

Abstract translation: 用于产生数字频率信号的数字合成器包括相位累加器，用于重复累加相位值以产生数字锯齿波信号的样本和用于将数字锯齿波信号转换为数字波形信号的数字采样的查找表。 为了减少数字样本量化的效果，合成器还包括随机化器，用于将随机化因子应用于输出用于形成数字频率信号的数字样本。 随机化器包括随机化因子发生器，其被连接以接收每个数字样本的P位以产生至少一个随机化位和用于对数字样本的剩余N位和至少一个随机化位进行求和的加法器，以产生数字波形样本 数字频率信号。

公开(公告)号：US5673212A

公开(公告)日：1997-09-30

申请号：US523099

申请日：1995-09-01

Applicant: Robert Karl Hansen

Inventor： Robert Karl Hansen

IPC: G06F1/03 ,  G06F1/02

CPC classification number: G06F1/0328

Abstract: A numerically controlled oscillator (NCO) (10) or direct digital synthesizer (DSS) includes a phase accumulator (12, 28, 30), a phase to amplitude converter (24), and a digital to analog converter (26). The phase accumulator is partitioned into a high speed phase accumulator stage (44) and a low speed phase accumulator stage (46). The high speed stage (44) performs modulo accumulation on the most significant N.sub.M bits of the entire phase word. The low speed stage (46) performs modulo accumulation on the least significant N.sub.L bits of the entire phase word. The low speed stage (46) supplies a carry signal to the high speed stage (44). The low speed stage (46) operates with an accumulation period that is 2.sup.X times slower than the accumulation period for the high speed stage (44). A phase output is taken from the most significant N.sub.p of the N.sub.M bits accumulated in the high speed stage (44), where desirably N.sub.M .gtoreq.N.sub.p +X.

Abstract translation: 数控振荡器（NCO）（10）或直接数字合成器（DSS）包括相位累加器（12,28,30），相位到幅度转换器（24）和数模转换器（26）。 相位累加器分为高速相位累加器级（44）和低速相位累加器级（46）。 高速级（44）对整个相位字的最重要的NM位执行模积累。 低速级（46）对整个相位字的最低有效NL位执行模积累。 低速级（46）向高速级（44）提供进位信号。 低速级（46）以比高速级（44）的累积周期慢2倍的累积周期运行。 相位输出取自在高速级（44）中积累的NM比特的最高有效Np，其中理想的是N N = N P + X。

公开(公告)号：US5563535A

公开(公告)日：1996-10-08

申请号：US350131

申请日：1994-11-29

Applicant: Alan Corry ,  Robert A. Sutherland

Inventor： Alan Corry ,  Robert A. Sutherland

IPC: G06F1/03 ,  H03C3/00 ,  H03B21/00

CPC classification number: H03C3/00 ,  G06F1/0328

Abstract: A direct digital synthesizer (DDS) for generating a waveform generates a sequence of n-bit phase signals representing phase of the waveform, wherein n is an integer greater than zero. Each n-bit phase signal comprises a phase estimate signal and a phase error signal. The phase estimate signal comprises a most-significant m bits of the n-bit quantity (0

Abstract translation: 用于产生波形的直接数字合成器（DDS）产生表示波形相位的n位相位信号的序列，其中n是大于零的整数。 每个n位相位信号包括相位估计信号和相位误差信号。 相位估计信号包括n比特量（0

公开(公告)号：US5428308A

公开(公告)日：1995-06-27

申请号：US162982

申请日：1993-12-08

Applicant: Kazuo Maeda

Inventor： Kazuo Maeda

IPC: H03B28/00 ,  G06F1/03 ,  H03L7/18 ,  H03K3/80

CPC classification number: H03L7/1806 ,  G06F1/0328

Abstract: A direct digital synthesizer which can be switched at a high speed and generates signals having a relatively high frequency with low power consumption; including a clock generator, a frequency setting circuit in which phase increment for unit clock can be programmed, a phase accumulator in which phase increment is accumulated, a ROM which outputs a digital signal corresponding to cumulative phase output, a D/A convertor which inverts polarity of output in each clock time, and a band-pass filter. The output of the band pass filter may be used as a reference input to a phase locked loop.

Abstract translation: 一种直接数字合成器，可以高速切换并产生具有低功耗的相对较高频率的信号; 包括时钟发生器，频率设定电路，其中可编程单位时钟的相位增量，累加相位增量的相位累加器，输出对应于累积相位输出的数字信号的ROM，反相的D / A转换器 每个时钟时间的输出极性和带通滤波器。 带通滤波器的输出可以用作锁相环的参考输入。

公开(公告)号：US5424667A

公开(公告)日：1995-06-13

申请号：US962974

申请日：1992-10-15

Applicant: Ryoichi Sakai ,  Iwao Akiyama ,  Yasumasa Fujisawa

Inventor： Ryoichi Sakai ,  Iwao Akiyama ,  Yasumasa Fujisawa

IPC: H03B28/00 ,  G06F1/03 ,  H03L7/18 ,  H03B19/00

CPC classification number: G06F1/0328 ,  G06F2101/04

Abstract: A DDS type variable frequency signal generator generates a jitter free and stable output signal regardless of the address interval. If the total number of addressable memory locations of a memory storing digital data is divisible without remainder by an initial address interval, then the memory is read every initial address interval with a clock signal of a predetermined frequency. If the total number of addressable memory locations is not divisible without remainder by the initial address interval, then the address interval is modified to a value that is divisible without remainder into the total number of addressable memory locations and the clock frequency is modified in accordance with this modification of the address interval. The memory is read every modified address interval with the modified clock signal.

Abstract translation: 无论地址间隔如何，DDS型可变频率信号发生器产生无抖动和稳定的输出信号。 如果存储数字数据的存储器的可寻址存储器位置的总数可被除以初始地址间隔的余数，则以每个初始地址间隔读取具有预定频率的时钟信号的存储器。 如果可寻址存储器位置的总数不能被除以初始地址间隔的余数，则地址间隔被修改为可以被除去的值，而没有余数到可寻址存储器位置的总数中，并且时钟频率根据 这个地址间隔的修改。 每个修改的地址间隔读取存储器与修改的时钟信号。