公开(公告)号：US06243247B1

公开(公告)日：2001-06-05

申请号：US09294853

申请日：1999-04-20

申请人： Omer Akdag ,  Ted K. Kulbieda ,  Roger Bishop

发明人： Omer Akdag ,  Ted K. Kulbieda ,  Roger Bishop

IPC分类号： H02H322

CPC分类号： H01Q1/50 ,  H01Q1/38

摘要： Apparatus for protecting electronic components and equipment and method of manufacturing the apparatus. A transient protection device capable of mounting onto a circuit board. The transient protection device includes first and second conductive paths. The first conductive path lies in a first plane and the second conductive path lies in a second plane spaced apart from the first plane. Furthermore, a dielectric material lies in a third plane disposed between the first and the second plane. A ground plane is coupled with said first conductive path to discharge an electrical surge.

摘要翻译： 用于保护电子部件和设备的装置及其制造方法。 一种能够安装到电路板上的瞬态保护装置。 瞬态保护装置包括第一和第二导电路径。 第一导电路径位于第一平面中，第二导电路径位于与第一平面间隔开的第二平面中。 此外，介电材料位于设置在第一和第二平面之间的第三平面中。 接地平面与所述第一导电路径耦合以放电电涌。

公开(公告)号：US06208493B1

公开(公告)日：2001-03-27

申请号：US08120998

申请日：1993-09-13

申请人： Charvaka Duvvury

发明人： Charvaka Duvvury

IPC分类号： H02H322

CPC分类号： H01L27/0251 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/49175 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A high-energy pulse protection device (10) protects an integrated circuit (28 and 30). The integrated circuit (28 and 30) is associated with an integrated circuit substrate region (64). The high-energy pulse protection device (10), has a protection circuit substrate region (74) that is disassociated from the integrated circuit substrate region (64). A primary protection circuit (40 and 42) is associated with the protection circuit substrate region (74) and has at least one connection (22) with the integrated circuit (28 and 30) for receiving and dissipating, through the at least one connection (22), a high-energy pulse. This protects the integrated circuit (28 and 30) from the high-energy pulse.

摘要翻译： 高能量脉冲保护装置（10）保护集成电路（28和30）。 集成电路（28和30）与集成电路衬底区域（64）相关联。 高能脉冲保护装置（10）具有与集成电路基板区域（64）分离的保护电路基板区域（74）。 主保护电路（40和42）与保护电路衬底区域（74）相关联并且具有与集成电路（28和30）的至少一个连接（22），用于通过至少一个连接（ 22），高能脉冲。 这保护了集成电路（28和30）免受高能脉冲的影响。

公开(公告)号：US06798629B1

公开(公告)日：2004-09-28

申请号：US09891906

申请日：2001-06-26

申请人： Robert J. Proebsting

发明人： Robert J. Proebsting

IPC分类号： H02H322

CPC分类号： H01L27/0266

摘要： Overvoltage protection circuits include a pass transistor having first and second current carrying terminals electrically connected to an input signal line and an output signal line, respectively, and a voltage clamping circuit. The voltage clamping circuit is electrically connected to a power supply line and a gate of the pass-transistor and dynamically clamps a capacitively bootstrapped voltage at a gate of the pass transistor within a first range so that the output voltage as well as the magnitudes of all gate-to-source, gate-to-drain and drain-to-source voltages across the pass transistor and all transistors within the voltage clamping circuit do not exceed a level in excess of about Vdd when Vin=2Vdd, where Vin equals a voltage of an input signal applied to the input signal line and Vdd equals a power supply voltage on the power supply line.

摘要翻译： 过电压保护电路包括分别具有电连接到输入信号线和输出信号线的第一和第二载流端子的通过晶体管和电压钳位电路。 电压钳位电路电连接到电源线和通过晶体管的栅极，并且在第一范围内动态地将传输晶体管的栅极处的电容性自举电压钳位，使得输出电压以及所有的幅度 栅极到源极，栅极到漏极和漏极到源极的电压跨过晶体管，并且当Vin = 2Vdd时，钳位电路内的所有晶体管不超过超过约Vdd的电平，其中Vin等于电压 施加到输入信号线的输入信号，Vdd等于电源线上的电源电压。

公开(公告)号：US06768616B2

公开(公告)日：2004-07-27

申请号：US10099600

申请日：2002-03-15

申请人： Markus Paul Josef Mergens ,  Cornelius Christian Russ ,  John Armer ,  Koen Gerard Maria Verhaege

发明人： Markus Paul Josef Mergens ,  Cornelius Christian Russ ,  John Armer ,  Koen Gerard Maria Verhaege

IPC分类号： H02H322

CPC分类号： H01L27/0262 ,  H01L27/0251 ,  H01L29/866 ,  H03K17/0812 ,  H03K17/0814 ,  H03K17/305

摘要： An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. In one embodiment, the ESD protection circuit includes a pad, adapted for connection to a protected circuit node of the IC, and an ESD protection device, which is coupled between the pad and ground. A diode turn-on device is coupled in a forward conduction direction from the pad to a first gate of the ESD protection device. In a second embodiment, the ESD protection circuit is an SCR having an anode coupled to a first voltage supply line, and a cathode coupled to ground. A parasitic capacitance is coupled between each the voltage supply line and the grounded cathode.

摘要翻译： 具有保护电路的半导体集成电路（IC）中的静电放电（ESD）保护电路。 在一个实施例中，ESD保护电路包括适于连接到IC的受保护电路节点的焊盘和耦合在焊盘和接地之间的ESD保护装置。 二极管导通装置从正面传导方向耦合到ESD保护装置的第一栅极。 在第二实施例中，ESD保护电路是具有耦合到第一电压供应线的阳极和耦合到地的阴极的SCR。 寄生电容耦合在每个电源线和接地阴极之间。

公开(公告)号：US06724602B2

公开(公告)日：2004-04-20

申请号：US09817970

申请日：2001-03-27

申请人： Demetri Giannopoulos

发明人： Demetri Giannopoulos

IPC分类号： H02H322

CPC分类号： H05B41/2851

摘要： A method and apparatus for fault condition protection for a lighting control circuit is presented. The method consists of a hybrid software and hardware solution to take advantage of the useful attributes of both. In the event of a fault condition being detected the software set driving signals to the light are rapidly blocked via hardware. In the event the fault condition persists, software modifies the driving signals to the light.

摘要翻译： 提出了一种用于照明控制电路的故障状态保护的方法和装置。 该方法由混合软件和硬件解决方案组成，以利用这两者的有用属性。 在检测到故障状态的情况下，通过硬件快速地阻止软件将驱动信号发送到光。 在故障状态仍然存在的情况下，软件将驱动信号修改为光。

公开(公告)号：US06717789B2

公开(公告)日：2004-04-06

申请号：US10008899

申请日：2001-12-05

申请人： Perry A. Holman ,  Jason M. Chilcote

发明人： Perry A. Holman ,  Jason M. Chilcote

IPC分类号： H02H322

CPC分类号： G01R17/10 ,  G01D3/032 ,  H02M1/12

摘要： A power supply rejection circuit and method thereof for capacitively-stored reference voltages is disclosed. The power supply rejection circuit generally comprises a comparison circuit for comparing a signal associated with a power supply such as, for example, a Wheatstone bridge configuration, to a stored reference voltage, such that the comparison circuit includes at least one existing capacitor therein. At least one additional capacitor can be then coupled to the comparison circuit, such that the additional capacitor creates a capacitively-coupled voltage divider. This capacitively-coupled voltage divider negates the first order effects of power supply noise in the system. This effect significantly reduces the effect of power supply noise and improves signal jitter associated with the comparison circuit during a comparison of the signal to the stored reference voltage utilizing the comparison circuit.

摘要翻译： 公开了一种用于电容存储的参考电压的电源抑制电路及其方法。 电源抑制电路通常包括比较电路，用于将与诸如惠斯通电桥配置的电源相关联的信号与存储的参考电压进行比较，使得比较电路在其中包括至少一个现有的电容器。 然后可以将至少一个附加电容器耦合到比较电路，使得附加电容器产生电容耦合分压器。 该电容耦合分压器消除了系统中电源噪声的一阶影响。 这种效应显着降低了电源噪声的影响，并且在利用比较电路比较信号与存储的参考电压之间，改善与比较电路相关联的信号抖动。

公开(公告)号：US06624998B2

公开(公告)日：2003-09-23

申请号：US09768715

申请日：2001-01-24

申请人： James Thomas May ,  Larry Earl Tyler

发明人： James Thomas May ,  Larry Earl Tyler

IPC分类号： H02H322

CPC分类号： H01L27/0292 ,  H01L27/0255 ,  H01L27/0266

摘要： Electrostatic Discharge (ESD) protection scheme includes a divided rail structure to route damaging ESD away from sensitive circuitry. Specifically, Vdd and Vss rails are divided to segregate the ESD current within a circuit, thus isolating the sensitive circuitry from ESD exposure. In an exemplary embodiment, Vdd is divided into Vdd-esd and Vdd core, while Vss is divided into Vss-esd and Vss core. The structure in cooperation with diodes, clamps and resistors enables to isolate the rails (Vdd core and Vss core) associated with sensitive circuitry from ESD current.

摘要翻译： 静电放电（ESD）保护方案包括一个分开的轨道结构，将有害ESD远离敏感电路。 具体来说，Vdd和Vss导轨被划分为隔离电路中的ESD电流，从而将敏感电路与ESD暴露隔离。 在示例性实施例中，Vdd被分为Vdd-esd和Vdd核，而Vss被分成Vss-esd和Vss核心。 与二极管，钳位和电阻配合使用的结构可以将与敏感电路相关的导轨（Vdd内核和Vss内核）与ESD电流隔离开来。

公开(公告)号：US06618233B1

公开(公告)日：2003-09-09

申请号：US09627090

申请日：2000-07-27

申请人： Christian Cornelius Russ ,  Koen Gerard Maria Verhaege ,  Leslie Ronald Avery

发明人： Christian Cornelius Russ ,  Koen Gerard Maria Verhaege ,  Leslie Ronald Avery

IPC分类号： H02H322

CPC分类号： H01L27/0262 ,  H01L27/0248 ,  H03K17/0403 ,  H03K17/0814

摘要： An ESD protection circuit includes a SCR and a switching means, such as a MOS transistor connected to the SCR so that the SCR is turned on by the switching means to allow an ESD pulse to pass from a Pad line to a grounded VSS line and thereby dissipate the ESD pulse. The SCR is connected between the Pad line and the VSS line. One MOS switching means is connected between the Pad line and the SCR and has a gate which is connected to a VDD line which maintains the switch in open condition during normal VDD bias conditions. An ESD pulse applied to the Pad line, the switch is preconditioned in ON mode allowing the SCR to be predisposed to conduction to allow the ESD pulse to flow to the VSS line.

摘要翻译： ESD保护电路包括SCR和诸如连接到SCR的MOS晶体管的开关装置，使得SCR由开关装置导通，以允许ESD脉冲从Pad线路传递到接地VSS线路，从而 耗散ESD脉冲。 SCR连接在Pad线和VSS线之间。 一个MOS开关装置连接在Pad线和SCR之间，并且具有连接到VDD线的栅极，其在正常VDD偏置条件期间将开关保持在断开状态。 施加到Pad线的ESD脉冲，开关在ON模式下被预处理，允许SCR倾向于导通，以允许ESD脉冲流向VSS线。

公开(公告)号：US06606231B2

公开(公告)日：2003-08-12

申请号：US10056934

申请日：2001-10-24

申请人： Mark Rumer

发明人： Mark Rumer

IPC分类号： H02H322

CPC分类号： H04M1/745 ,  H04M3/18

摘要： A protection device includes a substrate capable of suppressing electromagnetic fields, with a channel formed therein, a current dependent circuit interrupter disposed inside the channel, and voltage management circuitry coupled to the substrate. The voltage management circuitry is electrically coupled to the current dependent circuit interrupter so as to form a crowbar circuit in the presence of overvoltage or undervoltage conditions as determined according to a reference voltage.

公开(公告)号：US06556409B1

公开(公告)日：2003-04-29

申请号：US09652571

申请日：2000-08-31

申请人： Sailesh Chittipeddi ,  William Thomas Cochran ,  Yehuda Smooha

发明人： Sailesh Chittipeddi ,  William Thomas Cochran ,  Yehuda Smooha

IPC分类号： H02H322

CPC分类号： H01L23/60 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit that includes I/O circuitry that may or may not be protected from ESD damage. The protection from ESD damage may be selectively deactivated or activated or may not be present at all in one or more of the I/O circuits. In use, the integrated circuit may be coupled to another integrated circuit to form a multi-chip module where the ESD protection for the I/O circuitry between the modules is deactivated or not present. This is advantageous because the likelihood of ESD damage to this I/O circuitry is reduced once the multi-chip module is formed. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.

摘要翻译： 一个集成电路，其中包含I / O电路，可以或可能不受ESD保护。 可以选择性地禁用或激活对ESD损坏的保护，或者可以在一个或多个I / O电路中完全不存在。 在使用中，集成电路可以耦合到另一个集成电路以形成多芯片模块，其中模块之间的I / O电路的ESD保护被去激活或不存在。 这是有利的，因为一旦形成多芯片模块就可以减少对该I / O电路的ESD损坏的可能性。 应当理解，上述一般描述和以下详细描述都是本发明的示例性的，但不是限制性的。