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132 条记录 (耗时 0.017 秒)

    COMMUNICATION METHODS IN A NETWORK-ON-CHIP
    62.
    发明申请
    COMMUNICATION METHODS IN A NETWORK-ON-CHIP 有权

    公开(公告)号：US20220311699A1

    公开(公告)日：2022-09-29

    申请号：US17702118

    申请日：2022-03-23

    申请人： Airbus Defence and Space GmbH

    发明人： Sascha Uhrig ,  Johannes Freitag

    IPC分类号： H04L45/00 ,  H04L49/109

    摘要： A method for multi-source communication for triple-modular redundancy (TMR), a method for branched communication, and a method for virtual buses are disclosed. A method includes a) transmitting by at least two different source nodes in each case at least two identical messages which contain at least flow control data, payload data and check data to at least one predetermined receive node where the messages reach the receive node together at a predetermined time, b) combining by the receive node the messages received by the receive node into a combined message containing flow control data, payload data and check data, or comparing by the receive node of messages received by the receive node, and c) further processing of the combined message by the receive node or further processing of at least one of the messages received by the receive node based on comparison from step b).

    High speed debug hub for debugging designs in an integrated circuit
    63.
    发明授权
    High speed debug hub for debugging designs in an integrated circuit 有权

    公开(公告)号：US11442844B1

    公开(公告)日：2022-09-13

    申请号：US16889590

    申请日：2020-06-01

    申请人： Xilinx, Inc.

    发明人： Michael E. Peattie ,  Niloy Roy ,  Vishal Kumar Vangala

    IPC分类号： G06F11/00 ,  G06F11/36 ,  G06F11/27 ,  H04L49/109 ,  G01R31/3185 ,  G06F11/07

    摘要： An integrated circuit includes a high-speed interface configured to communicate with a host system for debugging and a debug hub coupled to the high-speed interface. The debug hub is configured to receive a debug command from the host system as memory mapped data. The integrated circuit also includes a plurality of debug cores coupled to the debug hub. Each debug core is coupled to the debug hub by channels. The debug hub is configured to translate the debug command to a data stream and provide the data stream to a target debug core of the plurality of debug cores based on an address specified by the debug command.

    Symbiotic Network On Layers
    66.
    发明申请
    Symbiotic Network On Layers 有权

    公开(公告)号：US20220150184A1

    公开(公告)日：2022-05-12

    申请号：US17583872

    申请日：2022-01-25

    申请人： Invensas Corporation

    发明人： Javier A. DeLaCruz ,  Belgacem Haba ,  Rajesh Katkar

    IPC分类号： H04L49/109

    摘要： The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

    Packet storage based on packet properties
    67.
    发明授权
    Packet storage based on packet properties 有权

    公开(公告)号：US12126549B2

    公开(公告)日：2024-10-22

    申请号：US18357710

    申请日：2023-07-24

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Sriramakrishnan Govindarajan ,  Mihir Narendra Mody

    IPC分类号： H04L49/90 ,  H04L49/109 ,  H04L67/568 ,  H04L69/22

    CPC分类号： H04L49/9042 ,  H04L49/109 ,  H04L67/568 ,  H04L69/22

    摘要： In an example, a system includes a network port that receives a packet; a first memory; a second memory; and a packet analyzer coupled to the network port. The packet analyzer operates to divide the packet into multiple fragments, analyze each of the multiple fragments to determine whether the corresponding fragment has a first priority level or a second, lower, priority level, determine whether to store each of the multiple fragments in the first memory or the second memory based on the priority level determined for that fragment, store each fragment determined to have the first priority level in the first memory, and store each fragment determined to have the second priority level in the second memory. The network port, packet analyzer and the first memory, which may be a cache memory, may be embodied on a chip, and the second memory may be external to the chip.

    Virtual Channel Buffer Bypass
    68.
    发明公开
    Virtual Channel Buffer Bypass 审中-公开

    公开(公告)号：US20240163222A1

    公开(公告)日：2024-05-16

    申请号：US18505478

    申请日：2023-11-09

    申请人： Graphcore Limited

    发明人： Ashley ROBINSON

    IPC分类号： H04L47/62 ,  H04L49/00 ,  H04L49/109

    CPC分类号： H04L47/6205 ,  H04L49/109 ,  H04L49/3018

    摘要： A bypass path is provided in the node for reducing the latency and power consumption associated with writing to and reading from the VC buffer, and is enabled when certain conditions are met. Bypass is enabled for a received packet when there is no other data that is ready to be sent from the VC buffer, which is the case when all VCs either have zero credits or an empty partition in the buffer. In this way, data arriving at the node is prevented from using the bypass path to take priority over data already held in the VC buffer and ready for transmission.

    Circuitry for Demarcation Devices and Methods Utilizing Same
    69.
    发明公开
    Circuitry for Demarcation Devices and Methods Utilizing Same 审中-公开

    公开(公告)号：US20240163209A1

    公开(公告)日：2024-05-16

    申请号：US18379941

    申请日：2023-10-13

    申请人： Sean Iwasaki

    发明人： Sean Iwasaki

    IPC分类号： H04L45/60 ,  H04L49/00 ,  H04L49/109 ,  H04L49/35

    CPC分类号： H04L45/60 ,  H04L49/109 ,  H04L49/30 ,  H04L49/355

    摘要： The present subject matter relates to methods, systems, devices, circuitry and equipment providing for communication service to be transported between first and second networks, and which monitors the communication service and/or injects test signals, and which can provide redundancy. At least one demarcation point or line is established between the first network and the second network, and/or between the first network, the second network and/or a third network. The Circuitry comprises a plurality of input amplifiers, output amplifiers, and multiplexer switches between a plurality of Port connectors. An SFP module or a WSFP module is inserted in the Ports.

    Composing diverse remote cores and FPGAs
    70.
    发明授权
    Composing diverse remote cores and FPGAs 有权

    公开(公告)号：US11973697B2

    公开(公告)日：2024-04-30

    申请号：US17572363

    申请日：2022-01-10

    申请人： Gray Research LLC

    发明人： Jan Stephen Gray

    IPC分类号： H04L12/28 ,  G06F13/42 ,  H04L12/18 ,  H04L49/109 ,  H04J1/16

    CPC分类号： H04L49/109 ,  G06F13/4282 ,  H04L12/18 ,  G06F2213/0026

    摘要： Embodiments of systems and methods for sending messages between cores across multiple field programmable gate arrays (FPGAs) and other devices are disclosed. A uniform destination address directs a message to a core in any FPGA. Message routing within one FPGA may use a bufferless directional 2D torus Network on Chip (NOC). Message routing between FPGAs may use remote router cores coupled to the NOCs. A message from one core to another in another FPGA is routed over a NOC to a local remote router then to external remote router(s) across inter-FPGA links or networks to the remote router of the second FPGA and across a second NOC to the destination core. Messages may also be multicast to multiple cores across FPGAs. A segmented directional torus NOC is also disclosed. The insertion of shortcut routers into directional torus rings achieves shorter ring segments, reducing message delivery latency and increasing NOC bandwidth.