公开(公告)号：US20240211408A1

公开(公告)日：2024-06-27

申请号：US18087887

申请日：2022-12-23

Applicant: INTEL CORPORATION

Inventor： JOYDEEP RAKSHIT ,  ANANT VITHAL NORI ,  SREENIVAS SUBRAMONEY ,  HANNA ALAM ,  JOSEPH NUZMAN

IPC: G06F12/0891 ,  G06F12/1009

CPC classification number: G06F12/0891 ,  G06F12/1009 ,  G06F2212/1016

Abstract: Apparatus and method for probabilistic cacheline replacement for accelerating address translation. For example, one embodiment of a processor comprises: a plurality of cores, each core to process instructions; a cache to be shared by a subset of the plurality of cores, the cache comprising an N-way set associative cache for storing page table entry (PTE) cachelines and non-PTE cachelines; and a cache manager to implement a PTE-aware eviction policy for evicting cachelines from the cache, the PTE-aware eviction policy to cause a reduction of evictions of PTE cachelines during non-PTE cacheline fills.

公开(公告)号：US20240211392A1

公开(公告)日：2024-06-27

申请号：US18434569

申请日：2024-02-06

Applicant: Intel Corporation

Inventor： Salma Mirza JOHNSON ,  Jose NIELL ,  Bradley A. BURRES ,  Jackson ELLIS ,  Yadong LI ,  Jayaram BHAT ,  Tony HURSON

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: Examples described herein relate to circuitry to allocate an Non-volatile Memory Express (NVMe) bounce buffer in virtual memory that is associated with an NVMe command and perform an address translation to an NVMe bounce buffer based on receipt of a response to the NVMe command from an NVMe target. In some examples, the circuitry is to translate the virtual address to a physical address for the NVMe bounce buffer based on receipt of a response to the NVMe command from an NVMe target.

公开(公告)号：US20240211297A1

公开(公告)日：2024-06-27

申请号：US18395766

申请日：2023-12-26

Applicant: Intel Corporation

Inventor： Zhao LIU ,  Zhenyu WANG

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45562

Abstract: A method for a primary virtual machine (VM) to schedule a sibling VM task executed by a hypervisor. Upon request of the sibling VM, the hypervisor creates a sibling task which includes a hypervisor ID. The hypervisor ID is then communicated to the primary VM. Subsequently, the primary VM creates a broker task, identified by its broker ID, and based on the received hypervisor ID for the sibling VM task. The primary VM then communicates to the hypervisor a mapping of the broker ID to the corresponding hypervisor ID. Finally, the primary VM executes the broker task when instructed by a scheduler of the primary VM. The broker task then triggers the hypervisor to run the corresponding sibling task based on the mapping.

公开(公告)号：US20240211258A1

公开(公告)日：2024-06-27

申请号：US18145770

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Yuvraj Dhillon ,  Doddaballapur Jayasimha ,  Aravindh V. Anantaraman ,  Yongsheng Liu

IPC: G06F9/30 ,  G06F11/34 ,  G06F12/02

CPC classification number: G06F9/30047 ,  G06F9/30189 ,  G06F11/3409 ,  G06F12/0246

Abstract: Remote atomics for clustered processing operations are described. An example of a graphics processor includes a clustered processing architecture including multiple clusters and one or more memory elements, including a first memory element containing a home agent, the apparatus to receive, at a first caching agent for a first cluster, a request for performance of an atomic operation requiring a data stored in a cacheline at a memory address associated with the home agent; evaluate one or more factors including a current ownership of the memory address; and, based at least in part on the factors, determine whether to perform the atomic operation at the first caching agent or to forward the atomic operation to the home agent for performance of the atomic operation.

公开(公告)号：US20240210835A1

公开(公告)日：2024-06-27

申请号：US18145035

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Joseph Bloxham

IPC: G03F7/40 ,  G03F7/20 ,  G03F7/32

CPC classification number: G03F7/40 ,  G03F7/32 ,  G03F7/70058

Abstract: Systems, apparatuses, and methods related to reducing the degradation of recycled developer solution are disclosed herein. In some embodiments, an apparatus may include a developer chamber, a process tank including a developer solution, a delivery stream coupling the process tank and the developer chamber to flow developer solution from the process tank to the developer chamber, a return stream coupling the developer chamber and the process tank to flow developer solution from the developer chamber to the process tank; and a light source exposing the developer solution to UV light or white light, wherein the light source exposes the developer solution to UV light or white light in the process tank, in the return stream, or the delivery stream.

公开(公告)号：US20240210821A1

公开(公告)日：2024-06-27

申请号：US18145038

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Charles Cameron Mokhtarzadeh ,  James Blackwell ,  Scott Semproni ,  Scott B. Clendenning ,  Lauren Elizabeth Doyle

IPC: G03F7/00 ,  G03F7/038 ,  G03F7/16 ,  G03F7/20 ,  G03F7/40

CPC classification number: G03F7/0032 ,  G03F7/038 ,  G03F7/162 ,  G03F7/167 ,  G03F7/2004 ,  G03F7/40

Abstract: Precursors and methods related to a bismuth oxy-carbide-based photoresist are disclosed herein. In some embodiments, a method for forming a bismuth oxy-carbide-based photoresist may include exposing a bismuth-containing precursor and a co-reagent to a substrate to form a bismuth oxy-carbide-based photoresist having a formula BixOyCz on the substrate, where x is 1 or 2, y is between 2 and 4, and z is between 1 and 5, the bismuth-containing precursor having a formula R′Bi(NR2)2 or R′2BiNR2 where R includes methyl, ethyl, isopropyl, tert-butyl, or trimethylsilyl, or NR2 is piperidine, and R′ includes methyl, ethyl, isopropyl, tert-butyl, cyclo-pentyl, cyclo-hexyl, methyl trimethylsilyl, methyl 2-butyl, benzyl, 1-methyl 2-dimethyl propyl, or cyclopentadienyl. In some embodiments, the co-reagent includes water, hydrogen peroxide, oxygen, ozone, formic acid, maleic acid, or an alcohol.

公开(公告)号：US20240210470A1

公开(公告)日：2024-06-27

申请号：US18089546

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Nir BONE ,  David TURJEMAN ,  Hussein DEEB

IPC: G01R31/3177 ,  G06F30/333

CPC classification number: G01R31/3177 ,  G06F30/333

Abstract: This disclosure describes systems, methods, and devices related to diagnose a broken scan chain and isolate the broken cell. A device may perform a functional test on a plurality of central processing unit (CPU) cells in a chain. The device may propagate data through a combinatoric logic. The device may capture results in sequential flip-flops associated with scan. The device may utilize the results in a next combinatoric logic. The device may utilize shifted-out data to isolate a first broken cell based on the functional test.

公开(公告)号：US12022323B2

公开(公告)日：2024-06-25

申请号：US17549728

申请日：2021-12-13

Applicant: Intel Corporation

Inventor： Katalin K. Bartfai-Walcott ,  Hassnaa Moustafa

IPC: H04W28/06 ,  H04L41/0896 ,  H04L41/5025 ,  H04L43/04 ,  H04L45/24 ,  H04L47/32 ,  H04L49/90 ,  H04L67/12 ,  H04W4/70 ,  H04W28/02 ,  H04L43/0852 ,  H04L43/0882 ,  H04L43/16 ,  H04L47/28 ,  H04L47/783 ,  H04L69/18 ,  H04W28/20 ,  H04W88/08 ,  H04W88/10

CPC classification number: H04W28/06 ,  H04L41/0896 ,  H04L41/5025 ,  H04L43/04 ,  H04L45/24 ,  H04L47/32 ,  H04L49/90 ,  H04L67/12 ,  H04W4/70 ,  H04W28/0231 ,  H04L43/0852 ,  H04L43/0882 ,  H04L43/16 ,  H04L47/28 ,  H04L47/783 ,  H04L69/18 ,  H04W28/20 ,  H04W88/08 ,  H04W88/10

Abstract: Disclosed embodiments relate to an orchestrator and arbitrator in an Internet of Things (IoT) platform. In one example, a method of servicing a plurality of data flows of a plurality of wireless devices using a plurality of protocols includes: monitoring one or more interfaces that communicate using the plurality of protocols, activating a first interface upon detecting a demand to exchange data thereon, wherein a connectivity manager performs the monitoring, and activating, extracting, by a packet analyzer, packet metadata from one or more of the plurality of data flows, determining latency encountered and bandwidth utilized by the one or more data flows based on the packet metadata, applying, by an adaptive connectivity manager (ACM), a latency reduction strategy to attempt to comply with latency criteria, and applying, by a bandwidth utilization manager (BUM), a bandwidth reduction strategy to attempt to comply with bandwidth criteria.

公开(公告)号：US12022013B2

公开(公告)日：2024-06-25

申请号：US17134363

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Prashant Dewan ,  Baiju Patel

IPC: H04L29/06 ,  G06F9/30 ,  H04L9/08 ,  H04L9/32

CPC classification number: H04L9/3278 ,  G06F9/30098 ,  G06F9/30145 ,  H04L9/0861 ,  H04L9/0894

Abstract: Techniques for encrypting data using a key generated by a physical unclonable function (PUF) are described. An apparatus according to the present disclosure may include decoder circuitry to decode an instruction and generate a decoded instruction. The decoded instruction includes operands and an opcode. The opcode indicates that execution circuitry is to encrypt data using a key generated by a PUF. The apparatus may further include execution circuitry to execute the decoded instruction according to the opcode to encrypt the data to generate encrypted data using the key generated by the PUF.

公开(公告)号：US12021720B2

公开(公告)日：2024-06-25

申请号：US16937267

申请日：2020-07-23

Applicant: Intel Corporation

Inventor： Ajay Gupta ,  Ravikumar Balakrishnan ,  Shahrnaz Azizi ,  Maruti Gupta Hyde ,  Ariela Zeira ,  Arjun Anand ,  Jacob Winick

IPC: H04L43/0852 ,  G06F1/3203 ,  H04L47/10 ,  H04L47/50

CPC classification number: H04L43/0852 ,  G06F1/3203 ,  H04L47/10 ,  H04L47/50

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that generate dynamic latency values. An example apparatus includes an active status controller to determine that a modem is active based on a number of packets obtained from a network, a prediction controller to predict that the number of packets are indicative of a workload type based on a trained model, and a latency value generator to generate a latency value based on the workload type of the number of packets, the latency value to cause a processor processing the number of packets to enter a power saving state or a power executing state.