公开(公告)号：US09645854B2

公开(公告)日：2017-05-09

申请号：US13287418

申请日：2011-11-02

Applicant: Benjamin Thomas Sander ,  Michael Houston ,  Newton Cheung ,  Keith Lowery

Inventor： Benjamin Thomas Sander ,  Michael Houston ,  Newton Cheung ,  Keith Lowery

IPC: G06F9/50 ,  G06T1/20

CPC classification number: G06F9/5044 ,  G06T1/20

Abstract: A method, system and article of manufacture for balancing a workload on heterogeneous processing devices. The method comprising accessing a memory storage of a processor of one type by a dequeuing entity associated with a processor of a different type, identifying a task from a plurality of tasks within the memory that can be processed by the processor of the different type, synchronizing a plurality of dequeuing entities capable of accessing the memory storage, and dequeuing the task form the memory storage.

公开(公告)号：US09639359B2

公开(公告)日：2017-05-02

申请号：US13976905

申请日：2013-05-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Yuan Xie ,  Junli Gu

IPC: G06F9/45 ,  G06F9/30 ,  G06F9/48

CPC classification number: G06F9/30083 ,  G06F8/4432 ,  G06F9/30087 ,  G06F9/30149 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D10/41

Abstract: Embodiments are described for a method for compiling instruction code for execution in a processor having a number of functional units by determining a thermal constraint of the processor, and defining instruction words comprising both real instructions and one or more no operation (NOP) instructions to be executed by the functional units within a single clock cycle, wherein a number of NOP instructions executed over a number of consecutive clock cycles is configured to prevent exceeding the thermal constraint during execution of the instruction code.

公开(公告)号：US09639280B2

公开(公告)日：2017-05-02

申请号：US14743091

申请日：2015-06-18

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0688

Abstract: The disclosed embodiments provide a system for processing a memory command on a computer system. During operation, a command scheduler executing on a memory controller of the computer system obtains a predicted latency of the memory command based on a memory address to be accessed by the memory command. Next, the command scheduler orders the memory command with other memory commands in a command queue for subsequent processing by a memory resource on the computer system based on the predicted latency of the memory command.

公开(公告)号：US20170102886A1

公开(公告)日：2017-04-13

申请号：US15386878

申请日：2016-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Daniel W. WONG

IPC: G06F3/06 ,  G06F13/12 ,  G06F13/40

CPC classification number: G06F3/0611 ,  G06F3/017 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/14 ,  G06F13/12 ,  G06F13/122 ,  G06F13/4072 ,  G09G2354/00 ,  G09G2360/08

Abstract: Methods, systems, and computer program products are provided for minimizing latency in a implementation where a peripheral device is used as a capture device and a compute device such as a GPU processes the captured data in a computing environment. In embodiments, a peripheral device and GPU are tightly integrated and communicate at a hardware/firmware level. Peripheral device firmware can determine and store compute instructions specifically for the GPU, in a command queue. The compute instructions in the command queue are understood and consumed by firmware of the GPU. The compute instructions include but are not limited to generating low latency visual feedback for presentation to a display screen, and detecting the presence of gestures to be converted to OS messages that can be utilized by any application.

公开(公告)号：US09621143B2

公开(公告)日：2017-04-11

申请号：US14076020

申请日：2013-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael J. Osborn ,  Michael J. Tresidder ,  Aaron J. Grenat ,  Joseph Kidd ,  Priyank Parakh ,  Steven J. Kommrusch

IPC: G06F9/455 ,  G06F17/50 ,  H03K5/153

CPC classification number: H03K5/153 ,  G06F17/5009 ,  G06F17/5031 ,  G06F2217/84

Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

公开(公告)号：US09619428B2

公开(公告)日：2017-04-11

申请号：US12476130

申请日：2009-06-01

Applicant: Michael J. Mantor ,  Brian Emberling

Inventor： Michael J. Mantor ,  Brian Emberling

IPC: G06F9/38 ,  G06F15/16 ,  G06F9/30 ,  G06T1/20

CPC classification number: G06F9/3009 ,  G06F9/30087 ,  G06F9/30098 ,  G06F9/30123 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F15/16 ,  G06F15/8007 ,  G06T1/20

Abstract: A graphics processing unit is disclosed, the graphics processing unit having a processor having one or more SIMD processing units, and a local data share corresponding to one of the one or more SIMD processing units, the local data share comprising one or more low latency accessible memory regions for each group of threads assigned to one or more execution wavefronts, and a global data share comprising one or more low latency memory regions for each group of threads.

公开(公告)号：US20170085472A1

公开(公告)日：2017-03-23

申请号：US14859844

申请日：2015-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Michael Ignatowski ,  Nuwan Jayasena ,  Gabriel H. Loh

IPC: H04L12/781 ,  H04L12/715 ,  H04L12/861 ,  H04L29/06

CPC classification number: H04L45/52 ,  H04L45/04 ,  H04L49/9057 ,  H04L69/08

Abstract: A communication device includes a data source that generates data for transmission over a bus, and a data encoder that receives and encodes outgoing data. An encoder system receives outgoing data from a data source and stores the outgoing data in a first queue. An encoder encodes outgoing data with a header type that is based upon a header type indication from a controller and stores the encoded data that may be a packet or a data word with at least one layered header in a second queue for transmission. The device is configured to receive at a payload extractor, a packet protocol change command from the controller and to remove the encoded data and to re-encode the data to create a re-encoded data packet and placing the re-encoded data packet in the second queue for transmission.

公开(公告)号：US09594521B2

公开(公告)日：2017-03-14

申请号：US14629014

申请日：2015-02-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Sergey Blagodurov ,  Andrew G. Kegel

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0647 ,  G06F3/0607 ,  G06F3/0611 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0659 ,  G06F3/067 ,  G06F12/0215 ,  G06F2212/654

Abstract: In one form, scheduling data migration comprises determining whether the data is likely to be used by an input/output (I/O) device, the data being at a location remote to the I/O device; and scheduling the data for migration from the remote location to a location local to the I/O device in response to determining that the data is likely to be used by the I/O device.

Abstract translation: 在一种形式中，调度数据迁移包括确定数据是否可能被输入/输出（I / O）设备使用，该数据位于远离I / O设备的位置; 并且响应于确定数据可能被I / O设备使用而调度用于从远程位置迁移到I / O设备本地的位置的数据。

公开(公告)号：US20170048320A1

公开(公告)日：2017-02-16

申请号：US15221554

申请日：2016-07-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini-Farahani ,  David A. Roberts

IPC: H04L29/08 ,  G06F3/06

CPC classification number: H04L67/1097

Abstract: Devices, methods, and systems for distributed gather and scatter operations in a network of memory nodes. A responding memory node includes a memory; a communications interface having circuitry configured to communicate with at least one other memory node; and a controller. The controller includes circuitry configured to receive a request message from a requesting node via the communications interface. The request message indicates a gather or scatter operation, and instructs the responding node to retrieve data elements from a source memory data structure and store the data elements to a destination memory data structure. The controller further includes circuitry configured to transmit a response message to the requesting node via the communications interface. The response message indicates that the data elements have been stored into the destination memory data structure.

Abstract translation: 在内存节点网络中进行分布式收集和分散操作的设备，方法和系统。 响应存储器节点包括存储器; 通信接口，其具有被配置为与至少一个其他存储器节点进行通信的电路; 和控制器。 控制器包括经配置以经由通信接口从请求节点接收请求消息的电路。 请求消息指示收集或散布操作，并指示响应节点从源存储器数据结构中检索数据元素，并将数据元素存储到目的地存储器数据结构。 控制器还包括经配置以经由通信接口向请求节点发送响应消息的电路。 响应消息指示数据元素已被存储到目的地存储器数据结构中。

公开(公告)号：US09563573B2

公开(公告)日：2017-02-07

申请号：US13970735

申请日：2013-08-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew T. Sobel

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/12 ,  G11C7/12 ,  G11C11/419

CPC classification number: G06F12/121 ,  G11C7/12 ,  G11C11/419

Abstract: A memory can be a sum addressed memory (SAM) that receives, for each read access, two address values (e.g. a base address and an offset) having a sum that indicates the entry of the memory to be read (the read entry). A decoder adds the two address value to identify the read entry. Concurrently, a predecode module predecodes the two address values to identify a set of entries (e.g. two different entries) at the memory, whereby the set includes the entry to be read. The predecode module generates a precharge disable signal to terminate precharging at the set of entries which includes the entry to be read. Because the precharge disable signal is based on predecoded address information, it can be generated without waiting for a full decode of the read address entry.

Abstract translation: 存储器可以是和寻址存储器（SAM），其针对每个读取访问接收具有指示要读取的存储器（读取条目）的条目的和的两个地址值（例如，基地址和偏移量）。 解码器将添加两个地址值以识别读取条目。 同时，预解码模块预先对两个地址值进行解码，以在存储器处标识一组条目（例如两个不同的条目），由此该集合包括要读取的条目。 预解码模块产生预充电禁止信号，以在包括要读取的条目的条目集合处终止预充电。 由于预充电禁止信号基于预解码的地址信息，所以可以在不等待读取地址条目的完全解码的情况下生成预充电禁止信号。