公开(公告)号：US08927909B2

公开(公告)日：2015-01-06

申请号：US12902005

申请日：2010-10-11

Applicant: Olivier Le Neel ,  Fuchao Wang ,  Ravi Shankar

Inventor： Olivier Le Neel ,  Fuchao Wang ,  Ravi Shankar

IPC: H05B1/02 ,  H05B3/12 ,  H05B3/34

CPC classification number: H05B3/0014 ,  H01L23/34 ,  H01L23/345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/15311 ,  H05B1/0227 ,  H05B3/02 ,  H05B3/06 ,  H05B3/12 ,  H05B3/34 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.

公开(公告)号：US08925835B2

公开(公告)日：2015-01-06

申请号：US12422690

申请日：2009-04-13

Applicant: Ming Fang ,  Fuchao Wang

Inventor： Ming Fang ,  Fuchao Wang

IPC: B05B1/24 ,  B41J2/16 ,  B41J2/14

CPC classification number: B41J2/1601 ,  B41J2/14056 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1639 ,  B41J2/1642 ,  B41J2/1643 ,  B41J2/1646 ,  B41J2002/1437 ,  B41J2202/16 ,  Y10T137/6416

Abstract: A method that includes forming a chamber in a substrate, forming a silicon layer overlying the chamber, etching the silicon layer to remove selected regions and retain a selected portion overlying the chamber, the selected portion being at a location and having dimensions that correspond to a location and to dimensions of a nozzle, and forming a first metal layer adjacent to the selected portion. The method also includes forming a path in the substrate to expose the chamber concurrently with removing the selected portion of the silicon layer to expose the nozzle, the nozzle being in fluid communication with the path, the chamber, and a surrounding environment.

Abstract translation: 一种方法，其包括在衬底中形成腔室，形成覆盖在所述腔室上的硅层，蚀刻所述硅层以去除所选择的区域并且保持覆盖所述腔室的选定部分，所述选定部分位于并且具有对应于 位置和尺寸，以及形成与选定部分相邻的第一金属层。 该方法还包括在衬底中形成路径以同时去除硅层的选定部分以暴露喷嘴，喷嘴与路径，腔室和周围环境流体连通。

公开(公告)号：US20140356990A1

公开(公告)日：2014-12-04

申请号：US13906447

申请日：2013-05-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Paul MIKULAN ,  Kenneth J. STEWART ,  Virginia L. HWANG

IPC: B41J2/335

CPC classification number: B41J2/1603 ,  B41J2/1601 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1635 ,  B41J2/1637 ,  B41J2/1639 ,  Y10T29/49083 ,  Y10T29/49087 ,  Y10T29/49401

Abstract: A method of making inkjet print heads may include forming a first wafer including a sacrificial substrate layer, and a first dielectric layer thereon having first openings therein defining inkjet orifices. The method may also include forming a second wafer having inkjet chambers defined thereon, and joining the first and second wafers together so that each inkjet orifice is aligned with a respective inkjet chamber. The method may further include removing the sacrificial substrate layer thereby defining the inkjet print heads.

Abstract translation: 制造喷墨打印头的方法可以包括形成包括牺牲基底层的第一晶片和其上具有限定喷墨孔的第一开口的第一介电层。 该方法还可以包括形成具有限定在其上的喷墨室的第二晶片，并且将第一和第二晶片接合在一起，使得每个喷墨孔与相应的喷墨室对准。 该方法还可以包括去除牺牲衬底层从而限定喷墨打印头。

公开(公告)号：US20140354736A1

公开(公告)日：2014-12-04

申请号：US13906466

申请日：2013-05-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Kenneth J. Stewart

IPC: B41J2/045 ,  B41J2/175

CPC classification number: B41J2/1433 ,  B41J2/16 ,  B41J2/1635 ,  B41J2202/20

Abstract: A method of making an inkjet print head may include forming, by sawing with a rotary saw blade, continuous slotted recesses in a first surface of a wafer. The continuous slotted recesses may be arranged in parallel, spaced apart relation, and each continuous slotted recess may extend continuously across the first surface. The method may further include forming discontinuous slotted recesses in a second surface of the wafer to be aligned and coupled in communication with the continuous slotted recesses to define alternating through-wafer channels and slotted recess portions. The method may further include selectively filling the residual slotted recess portions to define through-wafer ink channels.

Abstract translation: 制造喷墨打印头的方法可以包括通过用旋转锯片锯切在晶片的第一表面中形成连续的狭槽。 连续的开槽凹槽可以平行布置，间隔开的关系，并且每个连续的开槽凹槽可以连续延伸穿过第一表面。 该方法可以进一步包括在晶片的第二表面中形成不连续的开槽的凹槽，以与待连接的开槽的凹槽对准和耦合，以限定交替的晶片通道和开槽凹部。 该方法还可以包括选择性地填充剩余的开槽凹部以限定贯穿晶片墨水通道。

公开(公告)号：US20140340450A1

公开(公告)日：2014-11-20

申请号：US13893482

申请日：2013-05-14

Applicant: STMICROELECTRONICS ASIA PACIFIC PTE. LTD. ,  STMICROELECTRONICS, INC.

Inventor： MADANAGOPAL KUNNAVAKKAM ,  TECK KHIM NEO ,  KENNETH W. SMILEY

IPC: B41J2/14 ,  B41J2/16

CPC classification number: B41J2/14 ,  B41J2/14129 ,  B41J2/1603 ,  B41J2/1621 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/164

Abstract: An ink jet printhead device includes a substrate and at least one first dielectric layer above the substrate. A resistive layer is above the at least one first dielectric layer. An electrode layer is above the resistive layer and defines first and second electrodes coupled to the resistive layer. At least one second dielectric layer is above the electrode layer and contacts the resistive layer through the at least one opening. The at least one second dielectric layer has a compressive stress magnitude of at least 340 MPa.

Abstract translation: 喷墨打印头装置包括基底和在基底上方的至少一个第一介电层。 电阻层在至少一个第一介电层之上。 电极层位于电阻层之上，并且限定了耦合到电阻层的第一和第二电极。 至少一个第二电介质层在电极层之上，并且通过至少一个开口接触电阻层。 所述至少一个第二电介质层具有至少340MPa的压应力大小。

公开(公告)号：US08880976B2

公开(公告)日：2014-11-04

申请号：US12851465

申请日：2010-08-05

Applicant: Anthony Weathers

Inventor： Anthony Weathers

IPC: H03M13/00 ,  H03M13/11 ,  H03M13/29 ,  H03M13/35

CPC classification number: H03M13/2906 ,  H03M13/116 ,  H03M13/118 ,  H03M13/356

Abstract: Systems and methods for encoding and decoding at least one logical block address in a low density parity check (LDPC) are disclosed. These systems and methods can include selecting a LDPC Code matrix and a parity check matrix wherein the LDPC Code matrix and the parity check matrix have an orthogonal relationship. These systems and methods may further include encoding a data element using at least some of the LBA bits in the parity bits in a LDPC codeword creating a parity vector using the at least some of the LBA bits in the LDPC codeword.

Abstract translation: 公开了用于对低密度奇偶校验（LDPC）中的至少一个逻辑块地址进行编码和解码的系统和方法。 这些系统和方法可以包括选择LDPC码矩阵和奇偶校验矩阵，其中LDPC码矩阵和奇偶校验矩阵具有正交关系。 这些系统和方法还可以包括使用LDPC码字中的至少一些LBA比特，使用LDPC码字中的奇偶校验比特中的至少一些LBA比特来编码数据元素，从而产生奇偶校验向量。

公开(公告)号：US20140299938A1

公开(公告)日：2014-10-09

申请号：US13856325

申请日：2013-04-03

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Chengyu Niu ,  Heng Yang

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28132 ,  H01L21/2855 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7845 ,  H01L2924/04941 ,  H01L2924/0465 ,  H01L2924/04541 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/01029 ,  H01L2924/01022 ,  H01L2924/01007 ,  H01L2924/0505 ,  H01L2924/01013

Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.

Abstract translation: 增强载流子迁移率的方法和装置。 集成电路可以包括两种类型的半导体器件。 第一类型的装置可以包括金属门和以第一方式应变的通道。 第二类型的装置可以包括金属门和以第二方式应变的通道。 这些门可以共同地包括三种或更少的金属材料。 门可以共享相同的金属材料。 在集成电路上形成半导体器件的方法可以包括分别在对应于第一和第二栅极的集成电路的第一和第二区域中沉积第一和第二金属层。

公开(公告)号：US20140291750A1

公开(公告)日：2014-10-02

申请号：US13852720

申请日：2013-03-28

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Prasanna KHARE ,  Stephane Allegret-Maret ,  Nicolas Loubet ,  Qing Liu ,  Hemanth Jagannathan ,  Lisa Edge ,  Kangguo Cheng ,  Bruce Doris

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

Abstract: A memory device may include a semiconductor substrate, and a memory transistor in the semiconductor substrate. The memory transistor may include source and drain regions in the semiconductor substrate and a channel region therebetween, and a gate stack having a first dielectric layer over the channel region, a second dielectric layer over the first dielectric layer, a first diffusion barrier layer over the second dielectric layer, a first electrically conductive layer over the first diffusion barrier layer, a second diffusion barrier layer over the first electrically conductive layer, and a second electrically conductive layer over the second diffusion barrier layer. The first and second dielectric layers may include different dielectric materials, and the first diffusion barrier layer may be thinner than the second diffusion barrier layer.

Abstract translation: 存储器件可以包括半导体衬底和半导体衬底中的存储晶体管。 存储晶体管可以包括半导体衬底中的源极和漏极区域以及它们之间的沟道区域，以及栅极堆叠，其在沟道区域上具有第一介电层，在第一介电层上方具有第二介电层，第一扩散阻挡层 第一介电层，第一扩散阻挡层上的第一导电层，第一导电层上的第二扩散阻挡层，以及第二扩散阻挡层上的第二导电层。 第一和第二电介质层可以包括不同的电介质材料，并且第一扩散阻挡层可以比第二扩散阻挡层薄。

公开(公告)号：US08824432B2

公开(公告)日：2014-09-02

申请号：US12354593

申请日：2009-01-15

Applicant: Wendong Hu

Inventor： Wendong Hu

IPC: H04W4/00

CPC classification number: H04W48/12 ,  H04W16/14 ,  H04W28/26 ,  H04W72/1289

Abstract: A protocol for inter-cell communication in a cognitive radio wireless access network using beacon period framing is disclosed. By establishing scheduled use of beacon periods within each frame of a super-frame among a plurality of participating cells in a wireless access network, efficient and reliable communication can take place eliminating beacon packet collisions and bandwidth wastage. Within each super-frame exits 16 data frames of fixed size which can each include both a data transmission portion and a beacon period. A protocol is established by which announcement, reserved, and free-to-use beacon periods are established within the super-frames associated with a particular spectrum. By coordinating communication between cells on the beacon period, collision between cells by simultaneous attempts to transmit or bandwidth wastage of periods in which no transmission takes place can be avoided.

Abstract translation: 公开了一种使用信标周期框架的认知无线电无线接入网络中小区间通信的协议。 通过在无线接入网络中的多个参与小区中的超帧的每帧内建立信标周期的计划使用，可以发生有效和可靠的通信，消除信标分组冲突和带宽浪费。 在每个超帧内出现16个固定大小的数据帧，每个数据帧可以包括数据传输部分和信标周期。 建立通过在与特定频谱相关联的超帧内建立公告，保留和免费使用信标周期的协议。 通过协调信标周期之间的小区之间的通信，可以避免通过同时尝试发送的小区与不发生传输的周期的带宽浪费的冲突。

公开(公告)号：US08798448B2

公开(公告)日：2014-08-05

申请号：US12968150

申请日：2010-12-14

Applicant: Ming Fang ,  Fuchao Wang

Inventor： Ming Fang ,  Fuchao Wang

IPC: F24H1/20

CPC classification number: B81C1/00119 ,  B41J2/14056 ,  B41J2/14072 ,  B41J2/14137 ,  B41J2/16 ,  B41J2/1601 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1639 ,  B81B1/006 ,  B81B2201/052 ,  B81B2201/058 ,  B81C2201/013 ,  B81C2203/075 ,  H01L28/20 ,  Y10T29/41 ,  Y10T29/49401 ,  Y10T29/49826

Abstract: An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.

Abstract translation: 集成半导体加热组件包括半导体衬底，形成在其中的腔室以及与腔室流体连通的出口，允许流体响应于加热室而离开腔室。 集成加热组件包括邻近腔室的第一加热元件，该第一加热元件可以产生高于选定阈值的热量，并将腔室中的流体朝向出口偏压。 第二加热元件邻近出口定位以产生高于所选阈值的热量，便于流体通过出口远离腔室的运动。 添加第二加热元件减少了每个加热元件发出的热量，并使吸热材料的厚度最小化到出口的开口端。 由于这样的材料是昂贵的，所以这降低了组件的制造成本和零售价格，同时提高了其效率和使用寿命。