公开(公告)号：US08165117B2

公开(公告)日：2012-04-24

申请号：US11981409

申请日：2007-10-31

Applicant: Richard M. Wyatt

Inventor： Richard M. Wyatt

IPC: H04L12/56

CPC classification number: H04L45/74 ,  H04L45/745 ,  H04L45/7453 ,  H04Q3/68 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13103 ,  H04Q2213/13167

Abstract: A multistage switch includes a matrix of coupled switch devices. A logical link comprising a plurality of physical links couples a destination through the plurality of physical links to a plurality of ports in the multistage switch. Each switch device performs trunk aware forwarding to reduce the forwarding of received frames through the matrix of coupled switch devices to the destination in order to reduce unnecessary traffic in the multistage switch.

Abstract translation: 多级开关包括耦合开关器件的矩阵。 包括多个物理链路的逻辑链路通过多个物理链路将目的地耦合到多级交换机中的多个端口。 每个交换机设备执行中继线转发，以减少通过耦合的交换设备矩阵将接收的帧转发到目的地，以便减少多级交换机中的不必要的业务。

公开(公告)号：US20120096292A1

公开(公告)日：2012-04-19

申请号：US13239977

申请日：2011-09-22

Applicant: Nagi MEKHIEL

Inventor： Nagi MEKHIEL

IPC: G06F1/12 ,  G06F9/30 ,  G06F1/04

CPC classification number: G06F1/12 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/3851 ,  G06F9/3869 ,  G06F9/3887 ,  G06F9/526 ,  G06F15/76

Abstract: A Multi-Level Processor 200 for reducing the cost of synchronization overhead including an upper level processor 201 for taking control and issuing the right to use shared data and to enter critical sections directly to each of a plurality of lower level processors 202, 203 . . . 20n at processor speed. In one embodiment the instruction registers of lower level parallel processors are mapped to the data memory of upper level processor 201. Another embodiment 1300 incorporates three levels of processors. The method includes mapping the instructions of lower level processors into the memory of an upper level processor and controlling the operation of lower level processors. A variant of the method and apparatus facilitates the execution of Single Instruction Multiple Data (SIMD) and single to multiple instruction and multiple data (SI>MIMD). The processor includes the ability to stretch the clock frequency to reduce power consumption.

Abstract translation: 一种用于降低同步开销成本的多级处理器200，包括用于进行控制和发布使用共享数据的权利的上级处理器201，并且直接将关键部分输入到多个下级处理器202,203中的每一个。 。 。 20n处理器速度。 在一个实施例中，较低级并行处理器的指令寄存器被映射到上级处理器201的数据存储器。另一实施例1300包含三级处理器。 该方法包括将下级处理器的指令映射到上级处理器的存储器中并控制较低级处理器的操作。 方法和装置的一个变体便于执行单指令多数据（SIMD）和单指令到多指令和多数据（SI> MIMD）。 处理器包括延长时钟频率以降低功耗的能力。

公开(公告)号：US08145925B2

公开(公告)日：2012-03-27

申请号：US12210580

申请日：2008-09-15

Applicant: HakJune Oh

Inventor： HakJune Oh

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  G11C16/16 ,  G11C16/32 ,  Y02D10/14

Abstract: A non-volatile semiconductor memory device, which comprises (i) an interface having an input for receiving an input clock and a set of data lines for receiving commands issued by a controller including an erase command; (ii) a module having circuit components in a feedback loop configuration and being driven by a reference clock; (iii) a clock control circuit capable of controllably switching between a first state in which the reference clock tracks the input clock and a second state in which the reference clock is decoupled from the input clock; and (iv) a command processing unit configured to recognize the commands and to cause the clock control circuit to switch from the first state to the second state in response to recognizing the erase command. The module consumes less power when the reference clock is decoupled from the input clock than when the reference clock tracks the input clock.

Abstract translation: 一种非易失性半导体存储器件，其包括（i）具有用于接收输入时钟的输入的接口和用于接收由包括擦除命令的控制器发出的命令的一组数据线; （ii）具有反馈回路配置并由参考时钟驱动的电路部件的模块; （iii）时钟控制电路，其能够可控地在其中参考时钟跟踪输入时钟的第一状态和参考时钟与输入时钟去耦的第二状态之间切换; 以及（iv）命令处理单元，被配置为响应于识别所述擦除命令，识别所述命令并使所述时钟控制电路从所述第一状态切换到所述第二状态。 当参考时钟与输入时钟去耦时，该模块消耗的功率要小于参考时钟跟踪输入时钟时的功耗。

公开(公告)号：US08122218B2

公开(公告)日：2012-02-21

申请号：US13049487

申请日：2011-03-16

Applicant: Ian Mes

Inventor： Ian Mes

IPC: G06F12/00 ,  G06F1/12 ,  G06F1/00 ,  G11C8/00 ,  G11C8/16 ,  G11C8/18 ,  G11C7/00

CPC classification number: G11C7/1072 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract translation: 异步流水线SDRAM具有由异步信号控制的单独流水线级。 不是使用时钟信号在每个阶段同步数据，而是使用异步信号来锁存每个阶段的数据。 异步控制信号在芯片内产生，并针对不同的延迟级进行了优化。 更长的延迟阶段需要更大的延迟元件，而较短的等待时间状态需要更短的延迟元件。 在从芯片读出之前，数据与读取数据路径末端的时钟同步。 因为数据已经在每个流水线阶段被锁存，所以它比在传统的波形管线架构中看到的偏差更小。 此外，由于这些阶段与系统时钟无关，只要构建重新同步输出来支持读取数据路径，就可以以任何CAS延迟运行。

公开(公告)号：US08121132B2

公开(公告)日：2012-02-21

申请号：US11438259

申请日：2006-05-23

Applicant: Yehuda Binder

Inventor： Yehuda Binder

IPC: H04L12/56

CPC classification number: H04L41/0836 ,  G05B2219/21039 ,  G05B2219/25181 ,  H04L12/40 ,  H04L12/40019 ,  H04L12/403 ,  H04L12/42 ,  H04L12/66 ,  H04L49/40

Abstract: A network for carrying out control, sensing and data communications, comprising a plurality of nodes. Each node may be connected to a payload, which comprises sensors, actuators and DTE's. The network is formed using a plurality of independent communication links, each based on electrically-conducting communication media comprising at least two conductors and interconnecting two nodes, in a point-to-point configuration. During network operation, nodes can be dynamically configured as either data-generating nodes, wherein data is generated and transmitted into the network, or as receiver/repeater/router nodes, wherein received data is repeated from a receiver port to all output ports. During normal network operation, the network shifts from state to state. Each state is characterized by assigning a single node as the data-generating node, and configuring all other nodes in the network as repeaters and receivers. The network can be configured in linear or circular topology, or any mixture of both. The nodes and the payloads can each be powered by local power supply or via the network wiring. In the latter case, dedicated wires can be used, or the same conductors may be employed for both power distribution and communication. Network control can be performed external to the network, or by using the network itself as transport for control messages. Shifting from state to state can be done by selecting sequential nodes to be the data-generating node, or by selecting arbitrary nodes to be the data-generating node.

Abstract translation: 一种用于执行控制，感测和数据通信的网络，包括多个节点。 每个节点可以连接到有效载荷，其包括传感器，致动器和DTE。 网络使用多个独立的通信链路形成，每个通信链路基于包括至少两个导体并且以点到点配置互连两个节点的导电通信介质。 在网络操作期间，节点可以被动态地配置为数据生成节点，其中数据被生成并发送到网络，或者作为接收器/中继器/路由器节点，其中接收的数据从接收器端口重复到所有的输出端口。 在正常的网络运行过程中，网络从状态转移到状态。 每个状态的特征在于分配单个节点作为数据生成节点，并将网络中的所有其他节点配置为中继器和接收器。 网络可以配置为线性或圆形拓扑，或两者的任何混合。 节点和有效载荷每个都可以由本地电源或网络布线供电。 在后一种情况下，可以使用专用线，或者可以使用相同的导体来进行配电和通信。 网络控制可以在网络外部执行，也可以通过使用网络本身作为控制消息的传输。 可以通过选择顺序节点作为数据生成节点，或通过选择任意节点作为数据生成节点来实现从状态到状态的切换。

公开(公告)号：US08111607B2

公开(公告)日：2012-02-07

申请号：US11156140

申请日：2005-06-17

Applicant: D. J. Richard Van Nee

Inventor： D. J. Richard Van Nee

IPC: H04J11/00

CPC classification number: H04L27/2602 ,  H04L1/0002 ,  H04L5/1446 ,  H04L25/08 ,  H04L27/2605 ,  H04L27/2607 ,  H04L27/2647 ,  H04L27/2662

Abstract: An OFDM system uses a normal mode which has a symbol length T, a guard time TG and a set of N sub-carriers, which are orthogonal over the time T, and one or more fallback modes which have symbol lengths KT and guard times KTG where K is an integer greater than unity. The same set of N sub-carriers is used for the fallback modes as for the normal mode. Since the same set of sub-carriers is used, the overall bandwidth is substantially constant, so alias filtering does not need to be adaptive. The Fourier transform operations are the same as for the normal mode. Thus fallback modes are provided with little hardware cost. In the fallback modes the increased guard time provides better delay spread tolerance and the increased symbol length provides improved signal to noise performance, and thus increased range, at the cost of reduced data rate.

Abstract translation: OFDM系统使用具有在时间T上是正交的符号长度T，保护时间TG和一组N个子载波的正常模式，以及具有符号长度KT和保护时间KTG的一个或多个回退模式 其中K是大于1的整数。 相同的一组N个子载波用于回退模式，与正常模式一样。 由于使用相同的子载波集合，所以总带宽基本上是恒定的，所以别名滤波不需要是自适应的。 傅里叶变换操作与正常模式相同。 因此，回退模式的硬件成本很低。 在回退模式中，增加的保护时间提供更好的延迟扩展容限，并且增加的符号长度提供改善的信噪比性能，并因此提高范围，以降低的数据速率为代价。

公开(公告)号：US20120023286A1

公开(公告)日：2012-01-26

申请号：US13250301

申请日：2011-09-30

Applicant: Hong Beom PYEON ,  Jin-Ki Kim ,  HakJune Oh

Inventor： Hong Beom PYEON ,  Jin-Ki Kim ,  HakJune Oh

IPC: G06F12/00

CPC classification number: G06F13/4243 ,  G06F13/4247

Abstract: An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

Abstract translation: 提供了一种页面编程操作的装置和方法。 当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本 。 在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。 由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

公开(公告)号：US08102708B2

公开(公告)日：2012-01-24

申请号：US12884939

申请日：2010-09-17

Applicant: Jin-Ki Kim

Inventor： Jin-Ki Kim

IPC: G11C11/34

CPC classification number: G11C16/34 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.

Abstract translation: 用于多电平闪存单元的阈值电压分配方案，其中擦除阈值电压和至少一个编程的阈值电压位于擦除电压域中。 在擦除电压域中至少有一个编程的阈值电压降低了Vread电压电平，以最小化读取干扰效应，同时随着编程状态之间的阈值电压距离最大化，延长多电平闪存单元的使用寿命。 编程电压域大于0V时，擦除电压域可以小于0V。 因此，用于程序验证和读取具有在擦除电压域中的编程阈值电压和编程电压域的多电平闪存单元的电路使用负和正高电压。

公开(公告)号：US20120008426A1

公开(公告)日：2012-01-12

申请号：US13237202

申请日：2011-09-20

Applicant: Paul DEMONE

Inventor： Paul DEMONE

IPC: G11C7/10 ,  G11C7/00 ,  G11C7/12

CPC classification number: G11C11/405 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/18 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

Abstract translation: 动态随机存取存储器（DRAM）执行读，写和刷新操作。 DRAM包括多个子阵列，每个子阵列具有多个存储器单元，每个存储单元与互补位线对和字线耦合。 DRAM还包括用于断言所选择的一条字线的字线使能装置和用于断言所选位线对之一的列选择装置。 提供了一种定时电路，用于响应于字线定时脉冲来控制字线使能装置，列选择装置以及读，写和刷新操作。 读取，写入和刷新操作在相同的时间内执行。

公开(公告)号：US08095010B2

公开(公告)日：2012-01-10

申请号：US12087063

申请日：2005-12-28

Applicant: Luciano Socci ,  Paola Galli ,  Silvia Ghidini ,  Marco Romagnoli

Inventor： Luciano Socci ,  Paola Galli ,  Silvia Ghidini ,  Marco Romagnoli

IPC: H04J14/02

CPC classification number: G02B6/29343 ,  G02B6/12007 ,  G02B6/29355 ,  G02B6/29395 ,  H04J14/0204 ,  H04J14/0205 ,  H04J14/0206 ,  H04J14/021

Abstract: An optical device includes an optical splitter having an input port, a first output port, a second output port and a resonant structure including at least a resonator, the optical splitter being adapted to receive at the input port a WDM optical signal and to output at the first and second output ports, respectively, a first and a second portion of the optical signal, the second portion including the channels lying on a sub-grid of optical frequencies spaced by an integer multiple of the WDM frequency spacing; an optical combiner having a first input port, a second input port, an output port and adapted to receive at the first and second input ports, respectively, the first and the second portions and adapted to output them at said output port; a first optical path optically connecting the first output port of the optical splitter to the first input port of the optical combiner so as to propagate the first portion; a second optical path optically connecting the second output port of the optical splitter to the second input port of the optical combiner so as to propagate the second portion; and an optical filter optically coupled to the second optical path, wherein the optical combiner includes at least one resonant structure including at least a resonator.

Abstract translation: 光学装置包括具有输入端口，第一输出端口，第二输出端口和至少包括谐振器的谐振结构的光分路器，所述光分路器适于在输入端口处接收WDM光信号并在 所述第一和第二输出端口分别是所述光信号的第一和第二部分，所述第二部分包括位于与所述WDM频率间隔的整数倍间隔的光频率的子网格上的信道; 具有第一输入端口，第二输入端口，输出端口并适于在第一和第二输入端口分别接收第一和第二部分并适于在所述输出端口输出的光学组合器; 第一光路将光分路器的第一输出端口光学地连接到光组合器的第一输入端口，以便传播第一部分; 第二光路将光分路器的第二输出端口光学地连接到光组合器的第二输入端口，以便传播第二部分; 以及光学耦合到所述第二光路的光学滤波器，其中所述光合并器包括至少一个至少包括谐振器的谐振结构。