公开(公告)号：US5644529A

公开(公告)日：1997-07-01

申请号：US635455

申请日：1996-04-18

Applicant: Luigi Pascucci ,  Silvia Padoan

Inventor： Luigi Pascucci ,  Silvia Padoan

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C11/40

CPC classification number: G11C29/789 ,  G11C16/12 ,  G11C29/12

Abstract: In an integrated circuit for programming a memory cell in a non-volatile memory register which is associated with a memory matrix wherein the non-volatile memory register is used to store a redundancy address, the memory cell has at least one programmable non-volatile memory element having a control electrode and a data electrode and is suitable to store one bit of information. A load circuit associated to the memory element reads the information stored therein. The integrated circuit has switching means connected in series between the data electrode and a respective address signal line of an address signal bus which also supplies a decoding circuitry of the memory matrix. The switching means are controlled by a signal which determines the switching means to electrically connect the data electrode of the memory element to the address signal line when the memory cell of the non-volatile memory register is to be programmed, and to electrically disconnect the data electrode of the memory element from the address signal line when the information stored in the memory element is to be read by the load circuit.

Abstract translation: 在用于对与非易失性存储器寄存器用于存储冗余地址的存储器矩阵相关联的非易失性存储器寄存器中的存储器单元进行编程的集成电路中，存储器单元具有至少一个可编程非易失性存储器 元件具有控制电极和数据电极，并且适合于存储一位信息。 与存储器元件相关联的负载电路读取存储在其中的信息。 集成电路具有串联连接在数据电极和还提供存储器矩阵的解码电路的地址信号总线的相应地址信号线之间的开关装置。 开关装置由确定开关装置的信号控制，当非易失性存储寄存器的存储单元要被编程时，切换装置将存储元件的数据电极电连接到地址信号线，并且电连接数据 当存储在存储元件中的信息要由负载电路读取时，来自地址信号线的存储元件的电极。

公开(公告)号：US5637520A

公开(公告)日：1997-06-10

申请号：US195369

申请日：1994-02-10

Applicant: Paolo G. Cappelletti ,  Daniele Cantarelli

Inventor： Paolo G. Cappelletti ,  Daniele Cantarelli

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11526 ,  H01L27/11546 ,  H01L27/105 ,  Y10S438/981

Abstract: A process for simultaneously fabricating a flash-EEPROM memory and circuit transistors using a DPCC process. A first polysilicon layer is not removed from the circuit area, and the gate regions of a circuit transistors are formed by shorting first and second polysilicon layers. A thin tunnel oxide layer of the memory cells is formed using the same mask provided for implanting boron into the cell area of the substrate. Following implantation and without removing the mask, the gate oxide formed previously over the whole surface of the wafer is removed from the cell area; the boron implant mask is removed; and tunnel oxidation is performed to increase the thickness of the tunnel oxide by a desired amount, and to slightly increase the thickness of the oxide in the transistor area.

Abstract translation: 使用DPCC工艺同时制造闪存EEPROM存储器和电路晶体管的过程。 不从电路区域去除第一多晶硅层，并且通过使第一和第二多晶硅层短路来形成电路晶体管的栅极区域。 存储单元的薄隧道氧化物层使用用于将硼注入到衬底的单元区域中的相同掩模形成。 在注入并且不去除掩模之后，先前在晶片的整个表面上形成的栅极氧化物从电池区域中去除; 去除硼注入掩模; 并且进行隧道氧化以将隧道氧化物的厚度增加所需量，并且稍微增加晶体管区域中的氧化物的厚度。

公开(公告)号：US5631551A

公开(公告)日：1997-05-20

申请号：US348030

申请日：1994-12-01

Applicant: Salvatore Scaccianoce ,  Sergio Palara ,  Natale Aiello

Inventor： Salvatore Scaccianoce ,  Sergio Palara ,  Natale Aiello

IPC: G05F3/30 ,  G05F3/04

CPC classification number: G05F3/30

Abstract: A bandgap voltage reference circuit employs a Vbe voltage multiplier network in a feedback line of an output amplifier of the bandgap reference circuit, thus permitting to independently fix the output voltage that is produced and the temperature coefficient thereof. A voltage reference having a linear negative temperature coefficient in an extended temperature variation range may be obtained, starting from a bandgap reference voltage with a positive temperature coefficient.

Abstract translation: 带隙电压参考电路在带隙参考电路的输出放大器的反馈线路中使用Vbe电压倍增器网络，从而允许独立地固定所产生的输出电压及其温度系数。 从具有正温度系数的带隙基准电压开始，可以获得具有扩展温度变化范围内的线性负温度系数的电压基准。

公开(公告)号：US5631483A

公开(公告)日：1997-05-20

申请号：US509881

申请日：1995-08-01

Applicant: Giuseppe Ferla ,  Ferruccio Frisina

Inventor： Giuseppe Ferla ,  Ferruccio Frisina

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/76

CPC classification number: H01L29/7395

Abstract: A power device integrated structure includes a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type superimposed over the substrate, a plurality of first doped regions of the first conductivity type formed in the semiconductor layer, and a respective plurality of second doped regions of the second conductivity type formed inside the first doped regions. The power device includes: a power MOSFET having a fisrt electrode region formed by the second doped regions and a second electrode region formed by the semiconductor layer; a first bipolar junction transistor having an emitter, a base and a collector respectively formed by the substrate, the semiconductor layer and the first doped regions; and a second bipolar junction transistor having an emitter, a base and a collector respectively formed by the second doped regions, the first doped regions and the semiconductor layer. The doping profiles of the semiconductor substrate, the semiconductor layer, the first doped regions and the second doped regions are such that the first and second bipolar junction transistors have respective first and second common base current gains sufficiently high to cause the bipolar junction transistors to be biased in the high injection region, so that carriers are injected from the substrate into the semiconductor layer and from the second doped regions, through the first doped regions, into the semiconductor layer to modulate the conductivity of the second electrode of the power MOSFET; the fast and second common base current gains summed are less than unity to prevent a parasitic thyristor from triggering on.

Abstract translation: 功率器件集成结构包括第一导电类型的半导体衬底，叠加在衬底上的第二导电类型的半导体层，形成在半导体层中的多个第一导电类型的第一掺杂区和多个 形成在第一掺杂区域内的第二导电类型的第二掺杂区域。 功率器件包括：功率MOSFET，具有由第二掺杂区域形成的电极区域和由半导体层形成的第二电极区域; 第一双极结型晶体管，具有分别由衬底，半导体层和第一掺杂区域形成的发射极，基极和集电极; 以及分别由第二掺杂区域，第一掺杂区域和半导体层分别形成的发射极，基极和集电极的第二双极结型晶体管。 半导体衬底，半导体层，第一掺杂区域和第二掺杂区域的掺杂分布使得第一和第二双极结型晶体管具有足够高的相应的第一和第二公共基极电流增益，以使双极结型晶体管为 偏置在高注入区域中，使得载流子从衬底注入到半导体层中，并且从第二掺杂区域通过第一掺杂区域注入到半导体层中，以调制功率MOSFET的第二电极的导电性; 快速和第二共同基极电流增益相加均小于单位，以防止寄生晶闸管触发。

公开(公告)号：US5629610A

公开(公告)日：1997-05-13

申请号：US436947

申请日：1995-05-08

Applicant: Giorgio Pedrazzini ,  Giuseppe Scrocchi ,  Paolo Cordini ,  Domenico Rossi

Inventor： Giorgio Pedrazzini ,  Giuseppe Scrocchi ,  Paolo Cordini ,  Domenico Rossi

IPC: G05F1/56 ,  H02M1/08 ,  H02M3/155 ,  H02M3/156 ,  G05F1/563

CPC classification number: H02M3/156 ,  H02M3/1563

Abstract: A fully digital, current mode, PWM control is realized by employing two distinct comparators, both reading the voltage drop on a sensing resistance. The first comparator exerts an open-loop current mode control. The second comparator, establishing a second higher current threshold than the current threshold set by the first comparator, triggers a disabling circuit of the output power transistor for a preset period of time, when the current level through the output stage uncontrollably rises beyond the second threshold. This may occur because of an insufficient discharge from the load circuit inductance during off-phases of the output power transistor of the extra energy stored during switching delay periods of the first (open loop control) comparator. The frequency of the sequence of bursts may be precisely controlled to be well outside the frequency range of interest to prevent disturbances.

Abstract translation: 全数字电流模式通过采用两个不同的比较器来实现PWM控制，这两个比较器都读取感测电阻上的电压降。 第一个比较器进行开环电流模式控制。 第二比较器建立比由第一比较器设置的电流阈值更高的第二高电流阈值，在通过输出级的电流电平不可控地超过第二阈值时，触发输出功率晶体管的禁用电路达预设时间段 。 这可能是因为在第一（开环控制）比较器的开关延迟时段期间存储的额外能量的输出功率晶体管的非相位期间来自负载电路电感的不充分的放电。 突发序列的频率可以被精确地控制在很好的在感兴趣的频率范围之外，以防止干扰。

公开(公告)号：US5621361A

公开(公告)日：1997-04-15

申请号：US454922

申请日：1995-05-31

Applicant: Francesco Adduci

Inventor： Francesco Adduci

IPC: H03B5/36

CPC classification number: H03B5/364

Abstract: A one-pin integrated crystal oscillator in a Colpitts configuration employs a differential amplifier, provided with a feedback network, as an input gain stage. This achieves an enhanced stability and independence from temperature variation, a high Q figure, and a short start-up with a relatively small area of integration.

Abstract translation: Colpitts配置中的单针集成晶体振荡器采用带有反馈网络的差分放大器作为输入增益级。 这实现了增强的稳定性和独立于温度变化，高Q值以及具有相对小的积分面积的短启动。

公开(公告)号：US5621352A

公开(公告)日：1997-04-15

申请号：US517239

申请日：1995-08-21

Applicant: Edoardo Botti ,  Guido Brasca

Inventor： Edoardo Botti ,  Guido Brasca

IPC: H03F1/02 ,  H03F3/30 ,  H03F3/68 ,  H03F3/72

CPC classification number: H03F1/0277 ,  H03F3/3081 ,  H03F3/68 ,  H03F3/72

Abstract: A self-configurable, dual bridge, power amplifier has a window comparator sensing the level of input signals fed to the amplifier which-drives a plurality of configuring switches capable of configuring the amplifier as a single bridge amplifier driving a first and a second loads connected in series or as two distinct bridge amplifiers each driving one of the two loads. As long as the two levels of the input signals remain comprised between a range defined by a negative voltage reference and a positive voltage reference, the amplifier is configured as a single bridge driving the two loads in series, thus reducing sensibly power dissipation. Several embodiments of the configuring means are shown.

Abstract translation: 一个可自配置的双桥功率放大器具有一个窗口比较器，用于感测馈送到放大器的输入信号的电平，驱动多个配置开关，能够将放大器配置为单桥放大器，驱动第一和第二负载连接 串联或作为两个不同的桥式放大器驱动两个负载之一。 只要输入信号的两个电平保持在由负电压基准和正电压基准定义的范围之间，则放大器被配置为串联驱动两个负载的单个桥，因此降低了明智的功率耗散。 示出了配置装置的几个实施例。

公开(公告)号：US5619643A

公开(公告)日：1997-04-08

申请号：US414919

申请日：1995-03-31

Applicant: Angelo Moroni ,  Flavio Scarra ,  Alberto Taddeo

Inventor： Angelo Moroni ,  Flavio Scarra ,  Alberto Taddeo

IPC: G06F11/30 ,  G06F1/04 ,  G06F11/00 ,  H03K5/19

CPC classification number: G06F11/0757 ,  G06F1/04 ,  H03K5/19

Abstract: A circuit for generation of a reset signal in an electronic device, of the type comprising a microprocessor interlocked with a circuit generating a clock signal and memories of both the volatile type and the non-volatile type, is capable of detecting a stop in the oscillation of said clock signal and generating a logic signal coupled with the reset input of the microprocessor.

Abstract translation: 用于产生电子设备中的复位信号的电路，包括与产生时钟信号的电路互锁的微处理器以及易失型和非易失型两者的存储器的类型的电路能够检测振荡中的停止 并产生与微处理器的复位输入耦合的逻辑信号。

公开(公告)号：USRE35486E

公开(公告)日：1997-04-01

申请号：US390883

申请日：1995-02-09

Applicant: Franco Bertotti ,  Paolo Ferrari

Inventor： Franco Bertotti ,  Paolo Ferrari

IPC: H01L27/06 ,  H01L21/331 ,  H01L27/02 ,  H01L29/73 ,  H01L29/732 ,  H01L29/00

CPC classification number: H01L27/0248

Abstract: A circuital arrangement which comprises a vertical PNP transistor with insulated collector, which has a P-type collector structure surrounded by an N-type well and forms a junction therewith. In order to prevent latch-ups of the parasite SCR which is formed by the structure of the vertical transistor with insulated collector without limiting the voltage which can be applied between the collector and the emitter thereof to values below the intrinsic breakdown ones, the circuital arrangement comprises an auxiliary PNP transistor the emitter whereof is short-circuited with the emitter of the vertical PNP transistor, the base whereof is connected to the base of the vertical PNP transistor and the collector whereof is connected to the N-type well, and operates as a switch which biases the N-type well at a voltage which is close to the voltage of the emitter of the vertical PNP transistor when the latter is saturated, reverse-biasing the collector/N-well junction, and opens when the vertical PNP transistor is off, limiting. the voltage applied to the collector/N-well junction.

Abstract translation: 一种电路布置，其包括具有绝缘集电器的垂直PNP晶体管，其具有被N型阱包围并与其形成结的P型集电极结构。 为了防止由具有绝缘集电极的垂直晶体管的结构形成的寄生物SCR的闩锁，而不会将集电极和发射极之间施加的电压限制在低于固有击穿电压的值，则电路布置 包括一个辅助PNP晶体管，其发射极与垂直PNP晶体管的发射极短接，其基极连接到垂直PNP晶体管的基极，其集电极连接到N型阱，并作为 一个开关，当N型阱饱和时，垂直PNP晶体管的发射极的电压接近于N型阱，反向偏压集电极/ N阱结，当垂直PNP晶体管 是关闭，限制。 施加到集电极/ N阱结的电压。

公开(公告)号：US5614858A

公开(公告)日：1997-03-25

申请号：US180213

申请日：1994-01-12

Applicant: Alessio Pennisi

Inventor： Alessio Pennisi

IPC: H03H11/04 ,  H03H11/26 ,  H03K5/1252 ,  H03K5/08

CPC classification number: H03K5/1252

Abstract: A time delay filter includes at least one field-effect transistor of the MOS type and at least one bipolar transistor having their respective base and gate terminals connected together. The bipolar transistor is coupled to an input terminal through a drive transistor, and the field-effect transistor is coupled to an output terminal. The charge time for the gate capacitance of the field-effect transistor, using the low base current of the bipolar transistor, enables high-frequency noise to be filtered out of input digital signals.

Abstract translation: 时间延迟滤波器包括MOS型的至少一个场效应晶体管和至少一个双极晶体管，它们各自的基极和栅极端子连接在一起。 双极晶体管通过驱动晶体管耦合到输入端子，并且场效应晶体管耦合到输出端子。 使用双极晶体管的低基极电流，场效应晶体管的栅极电容的充电时间使得能够从输入数字信号中滤除高频噪声。