公开(公告)号：US08803596B2

公开(公告)日：2014-08-12

申请号：US14053189

申请日：2013-10-14

申请人： Tensorcom, Inc.

发明人： Zaw Soe

IPC分类号： H03H11/12 ,  H03F3/45 ,  H03F3/50 ,  H03H3/00 ,  H03F3/195 ,  H03F3/30

CPC分类号： H03H11/1217 ,  H03F3/195 ,  H03F3/301 ,  H03F3/45179 ,  H03F3/505 ,  H03F2203/45528 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03H3/00

摘要： Sallen-Key filters require an operational amplifier with a large input impedance and a small output impedance to meet the external filter characteristics. This invention eliminates the need for internal feedback path for stability and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6 dB of AC voltage gain and is substituted for the operational amplifier in the Sallen-Key filter. The Sallen-Key filter requires a differential configuration to generate all the required signals with their complements and uses these signals in a feed forward path. Furthermore, since the source follower uses only two n-channel stacked devices, the headroom voltage is maximized to several hundred millivolts for a 1.2V voltage supply in a 40 nm CMOS technology. Thus, the required 880 MHz bandwidth of the Sallen-Key filter can be easily met using the innovative source follower.

摘要翻译： Sallen-Key滤波器需要具有大输入阻抗和小输出阻抗的运算放大器，以满足外部滤波器特性。 本发明消除了对于稳定性的内部反馈路径的需要，并增加了具有与Sallen-Key滤波器中的运算放大器匹配的特性的源极跟随器的增益。 源极跟随器提供6 dB的交流电压增益，并代替Sallen-Key滤波器中的运算放大器。 Sallen-Key滤波器需要一个差分配置，以便产生所有需要的信号及其补码，并在前馈路径中使用这些信号。 此外，由于源极跟随器仅使用两个n沟道堆叠器件，因此在40nm CMOS技术中1.2V电压源的裕量电压最大可达数百毫伏。 因此，Sallen-Key滤波器所需的880 MHz带宽可以使用创新的源跟踪器轻松实现。

公开(公告)号：US08723602B2

公开(公告)日：2014-05-13

申请号：US13572522

申请日：2012-08-10

申请人： Jiashu Chen

发明人： Jiashu Chen

IPC分类号： H03F3/16

CPC分类号： H03F3/217 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15311 ,  Y02D70/20

摘要： The class-E amplifier can be tuned to pass only the fundamental frequency to the antenna by optimizing the second harmonics at the drain of the final PA driver transistor. A CPW in series with a capacitor between the PA transistor and the load forms a band pass filter that only allows the fundamental frequency to pass to the load of the antenna. A supply inductor to couple the drain of the final PA driver transistor to the power supply is tuned at the second harmonic with the parasitic capacitance of the drain of the PA transistor. A load capacitance is adjusted at the fundamental frequency to insure that the current waveform and voltage waveforms at the drain of the PA driver transistor do not overlap, thereby minimizing the parasitic power dissipation and allowing maximum energy to be applied to the antenna.

摘要翻译： 可以通过优化最终PA驱动器晶体管的漏极处的二次谐波，将E类放大器调谐为仅将基频通过天线。 与PA晶体管和负载之间的电容器串联的CPW形成只允许基频通过天线负载的带通滤波器。 将最终PA驱动器晶体管的漏极耦合到电源的电源电感器被调谐在具有PA晶体管的漏极的寄生电容的二次谐波处。 负载电容被调整到基频，以确保PA驱动晶体管的漏极处的电流波形和电压波形不重叠，从而最小化寄生功率耗散，并允许最大的能量施加于天线。

公开(公告)号：US08717215B2

公开(公告)日：2014-05-06

申请号：US13474743

申请日：2012-05-18

申请人： Dai Dai

发明人： Dai Dai

IPC分类号： H03M1/78

CPC分类号： H03M1/06 ,  H03M1/765

摘要： One of the critical design parameters occurs when a digital signal is converted into an analog signal. As the supply voltage drops to less than 2 times of threshold voltage to reduce leakage and save power, generating a relative large swing with a resistor-ladder DAC becomes more difficult. For a 5 bit DAC, 32 sub-arrays are used to select the appropriate voltage from the series coupled resistor network. Each sub-array uses p-channel transistors where the sub-array extracting the lowest voltage 700 mV only has a 100 mV of gate to source voltage. To compensate for the reduced gate to source voltage, the sub-arrays are partitioned into four groups. In each group, the p-channel width is increased from 2 um to 5 um, as the tap voltage drops from 1.2 V to 0.7 V. This allows the p-channel transistor with a small gate to source voltage to have a larger width thereby improving performance.

摘要翻译： 当数字信号转换为模拟信号时，出现关键设计参数之一。 由于电源电压下降到阈值电压的2倍以上以减少泄漏并节省功率，因此使用电阻梯形DAC产生相对较大的摆幅变得更加困难。 对于5位DAC，使用32个子阵列从串联电阻网络中选择合适的电压。 每个子阵列使用p沟道晶体管，其中提取最低电压700 mV的子阵列仅具有100 mV的栅极至源极电压。 为了补偿栅极到源极电压的降低，子阵列被分成四组。 在每组中，随着抽头电压从1.2V下降到0.7V，p沟道宽度从2um增加到5um。这允许具有较小栅极源极电压的p沟道晶体管具有较大的宽度， 提高性能。

公开(公告)号：US20140104007A1

公开(公告)日：2014-04-17

申请号：US14108329

申请日：2013-12-16

申请人： Tensorcom, Inc.

发明人： Syed Enam Rehman

IPC分类号： H03L7/00

CPC分类号： H03L7/00 ,  H03B1/00 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2200/0062 ,  H03L1/023 ,  H03L7/18

摘要： Capacitive adjustment in an RCL resonant circuit is typically performed by adjusting a DC voltage being applied to one side of the capacitor. One side of the capacitor is usually connected to either the output node or the gate of a regenerative circuit in an RCL resonant circuit. The capacitance loading the resonant circuit becomes a function of the DC voltage and the AC sinusoidal signal generated by the resonant circuit. By capacitively coupling both nodes of the capacitor, a DC voltage can control the value of the capacitor over the full swing of the output waveform. In addition, instead of the RCL resonant circuit driving a single differential function loading the outputs, each output drives an independent single ended function: thereby providing two simultaneous operations being determined in place of the one differential function.

摘要翻译： RCL谐振电路中的电容调整通常通过调整施加到电容器一侧的直流电压来进行。 电容器的一侧通常连接到RCL谐振电路中的再生电路的输出节点或栅极。 谐振电路的电容成为由谐振电路产生的直流电压和交流正弦信号的函数。 通过电容耦合电容器的两个节点，DC电压可以在输出波形的全摆幅时控制电容器的值。 此外，代替RCL谐振电路驱动负载输出的单个差分功能，每个输出驱动独立的单端功能：从而提供两个同时操作来代替一个差分功能。

公开(公告)号：US20140097894A1

公开(公告)日：2014-04-10

申请号：US14108312

申请日：2013-12-16

申请人： Tensorcom, Inc.

发明人： Zaw Soe

IPC分类号： H03F3/387

CPC分类号： H03F1/42 ,  H03D7/125 ,  H03D7/1441 ,  H03D7/1466 ,  H03D7/165 ,  H03F1/223 ,  H03F3/193 ,  H03F3/387 ,  H03F3/45071 ,  H03F3/45179 ,  H03F2200/108 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H03F2200/72 ,  H03F2200/75 ,  H04L27/38

摘要： A cascode common source and common gate LNAs operating at 60 GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra.

摘要翻译： 引入并描述了以60GHz操作的共源共栅和公共栅极LNA。 对共源共栅源LNA进行模拟，以达到上部器件宽度与较低器件宽度的最佳比例。 共源共栅源LNA的电压输出转换为电流以馈送并将能量施加到混频器级。 这些输入电流信号将与电流相关联的能量直接施加到混频器中的开关电容器中，以最小化系统的总功耗。 LNA电容耦合到I和Q混频器中的混频器开关，并由正交振荡器产生的时钟使能和禁止。 然后，这些信号被差分放大器放大以产生和和差频谱。

公开(公告)号：US20140091869A1

公开(公告)日：2014-04-03

申请号：US13632173

申请日：2012-10-01

申请人： TENSORCOM, INC.

发明人： KhongMeng Tham

IPC分类号： H03L5/00

CPC分类号： H03B5/364 ,  H03B5/06 ,  H03B2200/0088 ,  H03B2200/0094 ,  H03B2201/031 ,  H03L5/00

摘要： A large gain is used to start up the oscillation of the crystal quickly. Once the oscillation starts, the amplitude is detected. A control circuit determines based on the measured amplitude to disable a low resistance path in the controlled switch array to reduce the applied gain below the power dissipation specification of the crystal. Another technique introduces a mixed-signal controlled power supply multi-path resistive array which tailors the maximum current to the crystal. A successive approximation register converts the amplitude into several partitions and enables/disables one of several power routing paths to the inverter of the oscillator. This allows a better match between the crystal selected by the customer and the on-chip drive circuitry to power up the oscillator without stressing the crystal. The “l/f” noise of the oscillator circuit is minimized by operating transistors in the triode region instead of the linear region.

摘要翻译： 使用大的增益快速启动晶体振荡。 一旦振荡开始，就检测振幅。 控制电路基于测量的幅度来确定禁用受控开关阵列中的低电阻路径，以将施加的增益降低到低于晶体的功率耗散规格。 另一种技术引入了一种混合信号控制电源多路径电阻阵列，可以调整晶体的最大电流。 逐次逼近寄存器将振幅转换成几个分区，并使能/禁用振荡器的反相器的几个电源路由路径之一。 这允许由客户选择的晶体和片上驱动电路之间更好地匹配，以在不强调晶体的情况下加电振荡器。 通过在三极管区域中操作晶体管而不是线性区域来使振荡器电路的“l / f”噪声最小化。

公开(公告)号：US08674755B2

公开(公告)日：2014-03-18

申请号：US13916535

申请日：2013-06-12

申请人： Tensorcom, Inc.

发明人： Zaw Soe

IPC分类号： H03F3/45

CPC分类号： H03H11/1217 ,  H03F3/195 ,  H03F3/301 ,  H03F3/45179 ,  H03F3/505 ,  H03F2203/45528 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03H3/00

摘要： A differential amplifier comprising a first upper device and a first lower device series coupled between two power supplies and a second upper device and a second lower device series coupled between the two power supplies. A first DC voltage enables the first upper device and the second upper device and a second DC voltage regulates current flow in the first lower device and the second lower device. An AC signal component is coupled to the first upper device and the second lower device while the AC signal complement is coupled to the first lower device and the second upper device. Separate RC networks couple the AC signals to their respective device. A first and second output signal forms between the upper device and the lower device, respectively. All the devices are same channel type.

摘要翻译： 一种差分放大器，包括耦合在两个电源之间的第一上部装置和第一下部装置系列，以及耦合在两个电源之间的第二上部装置和第二下部装置。 第一直流电压使得第一上部装置和第二上部装置能够和第二直流电压调节第一下部装置和第二下部装置中的电流。 当AC信号补码耦合到第一下部装置和第二上部装置时，AC信号分量耦合到第一上部装置和第二下部装置。 单独的RC网络将AC信号耦合到其相应的设备。 分别在上部装置和下部装置之间形成第一和第二输出信号。 所有设备的通道类型相同。

公开(公告)号：US20140024328A1

公开(公告)日：2014-01-23

申请号：US13552955

申请日：2012-07-19

申请人： Joel Abe Balbien ,  HungYu David Yang ,  Thaddeus John Gabara

发明人： Joel Abe Balbien ,  HungYu David Yang ,  Thaddeus John Gabara

IPC分类号： H01Q21/00 ,  H04B7/00 ,  H01Q3/02

CPC分类号： H01Q21/293 ,  H01Q1/1257 ,  H01Q1/243 ,  H01Q1/38 ,  H01Q1/525 ,  H01Q3/04 ,  H01Q3/242 ,  H01Q9/16 ,  H01Q21/28 ,  H01Q25/00 ,  H01Q25/005 ,  H04B7/024

摘要： A portable unit with an endfire antenna and operating at 60 GHz makes an optimum communication channel with an endfire antenna in an array of antennas distributed over the area of a ceiling. The portable unit is pointed towards the ceiling and the system controlling the ceiling units selects and adjusts the positioning of an endfire antenna mounted on a 3-D adjustable rotatable unit. Several transceivers can be mounted together, offset from one another, to provide a wide coverage in both azimuth direction and elevation direction. These units can be rigidly mounted as an array in a ceiling apparatus. The system controlling the ceiling array selects one of the transceivers in one of the units to make the optimum communication channel to the portable unit. The system includes the integration of power management features by switching between Wi-Fi in favor of the 60 GHz channel.

摘要翻译： 具有端射天线并以60GHz操作的便携式单元与分布在天花板区域上的天线阵列中的端射天线形成最佳通信信道。 便携式设备被指向天花板，并且控制天花板单元的系统选择并调节安装在3-D可调节可旋转单元上的端面天线的定位。 几个收发器可以一起安装在一起，彼此偏移，以便在方位方向和仰角方向上提供广泛的覆盖。 这些单元可以作为阵列刚性地安装在天花板装置中。 控制天花板阵列的系统选择其中一个单元中的一个收发器，以将便携式单元的最佳通信信道。 该系统包括通过在支持60 GHz频道的Wi-Fi之间切换来集成电源管理功能。

公开(公告)号：US08626106B2

公开(公告)日：2014-01-07

申请号：US13312806

申请日：2011-12-06

申请人： Zaw Soe

发明人： Zaw Soe

IPC分类号： H04B1/16 ,  H03F3/19

CPC分类号： H03F1/42 ,  H03D7/125 ,  H03D7/1441 ,  H03D7/1466 ,  H03D7/165 ,  H03F1/223 ,  H03F3/193 ,  H03F3/387 ,  H03F3/45071 ,  H03F3/45179 ,  H03F2200/108 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H03F2200/72 ,  H03F2200/75 ,  H04L27/38

摘要： A cascode common source and common gate LNAs operating at 60 GHz are introduced and described. The cascode common source LNA is simulated to arrive at an optimum ratio of upper device width to the lower device width. The voltage output of the cascode common source LNA is translated into a current to feed and apply energy to the mixer stage. These input current signals apply the energy associated with the current directly into the switched capacitors in the mixer to minimize the overall power dissipation of the system. The LNA is capacitively coupled to the mixer switches in the I and Q mixers and are enabled and disabled by the clocks generated by the quadrature oscillator. These signals are then amplified by a differential amplifier to generate the sum and difference frequency spectra.

摘要翻译： 引入并描述了以60GHz操作的共源共栅和公共栅极LNA。 对共源共栅源LNA进行模拟，以达到上部器件宽度与较低器件宽度的最佳比例。 共源共栅源LNA的电压输出转换为电流以馈送并将能量施加到混频器级。 这些输入电流信号将与电流相关联的能量直接施加到混频器中的开关电容器中，以最小化系统的总功耗。 LNA电容耦合到I和Q混频器中的混频器开关，并由正交振荡器产生的时钟使能和禁止。 然后，这些信号被差分放大器放大以产生和和差频谱。

公开(公告)号：US20130307614A1

公开(公告)日：2013-11-21

申请号：US13474743

申请日：2012-05-18

申请人： Dai Dai

发明人： Dai Dai

IPC分类号： H03K5/00 ,  H01L25/00

CPC分类号： H03M1/06 ,  H03M1/765

摘要： One of the critical design parameters occurs when a digital signal is converted into an analog signal. As the supply voltage drops to less than 2 times of threshold voltage to reduce leakage and save power, generating a relative large swing with a resistor-ladder DAC becomes more difficult. For a 5 bit DAC, 32 sub-arrays are used to select the appropriate voltage from the series coupled resistor network. Each sub-array uses p-channel transistors where the sub-array extracting the lowest voltage 700 mV only has a 100 mV of gate to source voltage. To compensate for the reduced gate to source voltage, the sub-arrays are partitioned into four groups. In each group, the p-channel width is increased from 2 um to 5 um, as the tap voltage drops from 1.2 V to 0.7 V. This allows the p-channel transistor with a small gate to source voltage to have a larger width thereby improving performance.

摘要翻译： 当数字信号转换为模拟信号时，出现关键设计参数之一。 由于电源电压下降到阈值电压的2倍以上以减少泄漏并节省功率，因此使用电阻梯形DAC产生相对较大的摆幅变得更加困难。 对于5位DAC，使用32个子阵列从串联电阻网络中选择合适的电压。 每个子阵列使用p沟道晶体管，其中提取最低电压700 mV的子阵列仅具有100 mV的栅极至源极电压。 为了补偿栅极到源极电压的降低，子阵列被分成四组。 在每组中，随着抽头电压从1.2V下降到0.7V，p沟道宽度从2um增加到5um。这允许具有较小栅极源极电压的p沟道晶体管具有较大的宽度， 提高性能。