公开(公告)号：US20110182348A1

公开(公告)日：2011-07-28

申请号：US12693445

申请日：2010-01-26

Applicant: Chien-Chang Lin ,  Chan-Shih Lin

Inventor： Chien-Chang Lin ,  Chan-Shih Lin

IPC: H04N11/04 ,  G06F12/08

CPC classification number: H04N19/433 ,  H04N19/44 ,  H04N19/61

Abstract: Frame data stored in an external memory is partitioned into a plurality of macroblocks, and a plurality of access units each comprising at least one macroblock are provided. A plurality of frames are fetched from the external memory by loading the plurality of access units in a predetermined sequence. A current data for decoding a macroblock of the first access unit and a reference data for decoding a macroblock of the second access unit are loaded from the first access unit, and respectively mapped to a first memory group and a second memory group of a circular cache according to the frame width.

Abstract translation: 存储在外部存储器中的帧数据被划分为多个宏块，并且提供了包括至少一个宏块的多个存取单元。 通过以预定顺序加载多个访问单元，从外部存储器取出多个帧。 用于解码第一存取单元的宏块的当前数据和用于解码第二存取单元的宏块的参考数据从第一存取单元加载，分别映射到循环缓存的第一存储组和第二存储组 根据帧宽度。

公开(公告)号：US20110182312A1

公开(公告)日：2011-07-28

申请号：US12845855

申请日：2010-07-29

Applicant: Wei-Li Chen ,  Shih-Chang Lin

Inventor： Wei-Li Chen ,  Shih-Chang Lin

IPC: H01S5/343 ,  H01S5/34

CPC classification number: H01S5/34313 ,  B82Y20/00 ,  H01S5/3407 ,  H01S5/4043 ,  H01S2301/04

Abstract: A laser diode using asymmetric quantum wells includes a N-type semiconductor, a P-type semiconductor, a first quantum well structure, and a second quantum well structure. The first quantum well structure is between the N-type semiconductor and the P-type semiconductor, and includes at least one first quantum well having a first thickness. The second quantum well structure is between the N-type semiconductor and the P-type semiconductor, and includes at least one second quantum well having a second thickness greater than the first thickness of the first quantum well and a lasing wavelength greater than that of the first quantum well. The second quantum well is formed with a spike therein.

Abstract translation: 使用不对称量子阱的激光二极管包括N型半导体，P型半导体，第一量子阱结构和第二量子阱结构。 第一量子阱结构在N型半导体和P型半导体之间，并且包括具有第一厚度的至少一个第一量子阱。 第二量子阱结构在N型半导体和P型半导体之间，并且包括至少一个具有大于第一量子阱的第一厚度的第二厚度的第二量子阱，并且激光波长大于 第一量子阱。 第二量子阱在其中形成有尖峰。

公开(公告)号：US20110130007A1

公开(公告)日：2011-06-02

申请号：US12884609

申请日：2010-09-17

Applicant: CHI-HONG CHING ,  CHANG-LIN HSIEH ,  JIE ZHOU

Inventor： CHI-HONG CHING ,  CHANG-LIN HSIEH ,  JIE ZHOU

IPC: H01L21/467

CPC classification number: H01L21/32136 ,  H01J37/32862 ,  H01L21/02071 ,  H01L21/31144

Abstract: Methods of processing substrates having titanium nitride layers are provided. In some embodiments, a method for processing a substrate having a dielectric layer to be etched, a titanium nitride layer above the dielectric layer, and a patterned photoresist layer above the titanium nitride layer, includes etching a pattern into the titanium nitride layer by exposing the titanium nitride layer to a first plasma comprising a chlorine containing gas to form a hard mask; removing titanium nitride etch residues disposed on one or more surfaces of the process chamber and/or substrate by forming a second plasma in the process chamber from a reactive gas comprising at least one of carbon monoxide or carbon dioxide; and etching the dielectric layer through the hard mask with a third plasma comprising a fluorocarbon gas.

Abstract translation: 提供了处理具有氮化钛层的衬底的方法。 在一些实施例中，一种用于处理具有要蚀刻的介电层，在电介质层上方的氮化钛层和在氮化钛层上方的图案化的光致抗蚀剂层的衬底的方法包括通过将图案暴露于氮化钛层 氮化钛层至含有含氯气体的第一等离子体，形成硬掩模; 通过在包括至少一种一氧化碳或二氧化碳的反应性气体中在所述处理室中形成第二等离子体来去除设置在所述处理室和/或衬底的一个或多个表面上的氮化钛蚀刻残留物; 并用包含碳氟化合物气体的第三等离子体通过硬掩模蚀刻电介质层。

公开(公告)号：US20110124737A1

公开(公告)日：2011-05-26

申请号：US12965514

申请日：2010-12-10

Applicant: Chin-Ming Chang ,  James N. Chang ,  Rhett M. Schiffman ,  R. Scott Jordan ,  Joan-En Chang-Lin

Inventor： Chin-Ming Chang ,  James N. Chang ,  Rhett M. Schiffman ,  R. Scott Jordan ,  Joan-En Chang-Lin

IPC: A61K31/165 ,  A61P27/02 ,  A61P27/06

CPC classification number: A61K31/5575 ,  A01N33/12 ,  A61K9/0048 ,  A61K31/14 ,  A61K31/165 ,  A61K31/557 ,  A61K47/02 ,  A61K47/12

Abstract: A composition comprising from 0.005% to 0.02% bimatoprost by weight and from 100 ppm to 250 ppm benzalkonium chloride, wherein said composition is an aqueous liquid which is formulated for ophthalmic administration is disclosed herein.A method which is useful in treating glaucoma or ocular hypertension related thereto is also disclosed herein.

Abstract translation: 本文公开了包含0.005％至0.02％的比马前列素和100ppm至250ppm苯扎氯铵的组合物，其中所述组合物是配制用于眼部给药的水性液体。 本文还公开了可用于治疗与其有关的青光眼或高眼压症的方法。

公开(公告)号：US20110117710A1

公开(公告)日：2011-05-19

申请号：US12621518

申请日：2009-11-19

Applicant: Yung-Chang Lin ,  Kuei-Sheng Wu ,  Chang-Chien Wong ,  Ching-Hsiang Tseng

Inventor： Yung-Chang Lin ,  Kuei-Sheng Wu ,  Chang-Chien Wong ,  Ching-Hsiang Tseng

IPC: H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L27/0629 ,  H01L29/7848

Abstract: A method of fabricating an efuse, a resistor and a transistor includes the following steps: A substrate is provided. Then, a gate, a resistor and an efuse are formed on the substrate, wherein the gate, the resistor and the efuse together include a first dielectric layer, a polysilicon layer and a hard mask. Later, a source/drain doping region is formed in the substrate besides the gate. After that, the hard mask in the resistor and the efuse is removed. Subsequently, a salicide process is performed to form a silicide layer on the source/drain doping region, the resistor, and the efuse. Then, a planarized second dielectric layer is formed on the substrate and the polysilicon in the gate is exposed. Later, the polysilicon in the gate is removed to form a recess. Finally a metal layer is formed to fill up the recess.

Abstract translation: 一种制造efuse，电阻器和晶体管的方法包括以下步骤：提供衬底。 然后，在衬底上形成栅极，电阻器和efuse，其中栅极，电阻器和efuse一起包括第一介电层，多晶硅层和硬掩模。 之后，在栅极之外的基板中形成源极/漏极掺杂区域。 之后，去除电阻和efuse中的硬掩模。 随后，执行自对准硅化处理以在源/漏掺杂区域，电阻器和efuse上形成硅化物层。 然后，在基板上形成平坦化的第二介质层，露出栅极中的多晶硅。 之后，去除栅极中的多晶硅以形成凹陷。 最后，形成一个金属层以填充凹槽。

公开(公告)号：US20110069147A1

公开(公告)日：2011-03-24

申请号：US12690848

申请日：2010-01-20

Applicant: CHIEN-CHANG LIN ,  PI-JYE TSAUR

Inventor： CHIEN-CHANG LIN ,  PI-JYE TSAUR

IPC: H04N7/00

CPC classification number: G03B37/04 ,  H04N5/2251 ,  H04N7/183 ,  H04N19/597 ,  H04N2101/00

Abstract: A panoramic camera, a system, and a method for monitoring target places using the panoramic camera are provided. The system includes a network access server (NAS) connected to the panoramic camera, a video decoder, a computer workstation, and a monitor screen. The panoramic camera captures digital images of a target place from different viewing angles, combines the digital images to create a panoramic image of the target place, encodes and compresses the panoramic image to generate an encoded panoramic image, and transmits the encoded panoramic image to the NAS through a network. When the target place needs to be monitored, the computer workstation obtains the encoded panoramic image from the NAS through a hub. The video decoder decodes the encoded panoramic image to retrieve the panoramic image of the target place. The monitor screen displays the panoramic image to a user for viewing and monitoring the target place.

Abstract translation: 提供全景相机，系统以及使用全景相机监视目标地点的方法。 该系统包括连接到全景相机的网络接入服务器（NAS），视频解码器，计算机工作站和监视器屏幕。 全景相机从不同的视角捕获目标地点的数字图像，组合数字图像以创建目标位置的全景图像，对全景图像进行编码和压缩以生成编码的全景图像，并将编码的全景图像发送到 NAS通过网络。 当需要监视目标地点时，计算机工作站通过集线器从NAS获取编码的全景图像。 视频解码器解码编码的全景图像以检索目标地点的全景图像。 监视器屏幕将向用户显示全景图像以查看和监视目标位置。

公开(公告)号：US07911318B2

公开(公告)日：2011-03-22

申请号：US11707539

申请日：2007-02-16

Applicant: Chin-Sun Shyu ,  Chang-Sheng Chen ,  Chang-Lin Wei ,  Wei-Ting Chen

Inventor： Chin-Sun Shyu ,  Chang-Sheng Chen ,  Chang-Lin Wei ,  Wei-Ting Chen

IPC: H01C1/012

CPC classification number: H01C1/02 ,  H01C7/006 ,  H01C10/46 ,  H01C17/00 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/167 ,  H05K3/429 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2203/171

Abstract: The present invention relates to an adjustable resistor embedded in a circuit board and a method of fabricating the same. The adjustable resistor comprises a resistor with a number of connection terminals, and a number of via holes extending to contact with the resistor. The resistive value of the resistor is variable depending on the size of the via holes, the number of the via holes, or the distance between the via holes.

Abstract translation: 本发明涉及嵌入在电路板中的可调电阻器及其制造方法。 可调电阻器包括具有多个连接端子的电阻器以及延伸以与电阻器接触的多个通孔。 电阻器的电阻值根据通孔的尺寸，通孔的数量或通孔之间的距离而变化。

公开(公告)号：US07884697B2

公开(公告)日：2011-02-08

申请号：US12037622

申请日：2008-02-26

Applicant: Chang-Lin Wei ,  Cheng-Hua Tsai ,  Chin-Sun Shyu ,  Kuo-Chiang Chin ,  Syun Yu

Inventor： Chang-Lin Wei ,  Cheng-Hua Tsai ,  Chin-Sun Shyu ,  Kuo-Chiang Chin ,  Syun Yu

IPC: H01F5/00

CPC classification number: H01F21/12 ,  H01F17/0006 ,  H01F41/045 ,  H01F2017/002 ,  H01F2021/125

Abstract: The invention provides tunable embedded high frequency inductor devices. The inductor device comprises a dielectric substrate. A first conductive line is disposed on a first surface of the dielectric substrate. A second conductive line is disposed on a second surface of the dielectric substrate. An interconnection is disposed perforating the dielectric substrate and connecting the first conductive line with the second conductive line. A coupling region is defined between the first and the second conductive lines. A conductive plug connecting the first conductive line and the second line is disposed in the coupling region. Alternatively, an opening is disposed in the first and second conductive lines to tune inductance of the inductor.

Abstract translation: 本发明提供可调谐嵌入式高频电感器件。 电感器件包括电介质基片。 第一导电线设置在电介质基板的第一表面上。 第二导电线设置在电介质基板的第二表面上。 互连被布置成穿过电介质基板并将第一导电线与第二导电线连接。 在第一和第二导线之间限定耦合区域。 连接第一导线和第二线的导电插头设置在耦合区域中。 或者，开口设置在第一和第二导线中以调谐电感器的电感。

公开(公告)号：US20100321308A1

公开(公告)日：2010-12-23

申请号：US12545449

申请日：2009-08-21

Applicant: HSIEN CHANG LIN ,  HSIANG JUI WANG

Inventor： HSIEN CHANG LIN ,  HSIANG JUI WANG

IPC: G06F3/041

CPC classification number: G06F3/044

Abstract: A touch panel includes a transparent substrate having a surface, a plurality of first touch sensor pads arrayed in a matrix on the surface, a plurality of second touch sensor pads arrayed in a matrix and staggered between the plurality of first touch sensor pads, a dielectric layer disposed upon the plurality of first touch sensor pads and the plurality of second touch sensor pads, a plurality of third touch sensor pads arrayed in a matrix on the dielectric layer, and a plurality of fourth touch sensor pads arrayed in a matrix on the dielectric layer and staggered between the plurality of third touch sensor pads. Each first touch sensor pad includes a first hollowed-out pattern, and each third touch sensor pad includes a second hollowed-out pattern and a solid portion formed around the second hollowed-out pattern, wherein a portion of the solid portion of each third touch sensor pad and a portion of the hollowed-out pattern of the first touch sensor pad overlap.

Abstract translation: 触摸面板包括具有表面的透明衬底，在表面上以矩阵形式排列的多个第一触摸传感器焊盘，排列成矩阵并交错在多个第一触摸传感器焊盘之间的多个第二触摸传感器焊盘，电介质 层，设置在所述多个第一触摸传感器焊盘和所述多个第二触摸传感器焊盘上，多个第三触摸传感器焊盘以矩阵形式布置在所述电介质层上，以及多个第四触摸传感器焊盘，其被布置在所述电介质上的矩阵中 并且在多个第三触摸传感器焊盘之间交错。 每个第一触摸传感器焊盘包括第一镂空图案，并且每个第三触摸传感器焊盘包括第二中空图案和围绕第二镂空图案形成的实心部分，其中每个第三触摸的实心部分的一部分 传感器垫和第一触摸传感器垫的镂空图案的一部分重叠。

公开(公告)号：USD624312S1

公开(公告)日：2010-09-28

申请号：US29322342

申请日：2008-08-01

Applicant: David Ching Chi Chu ,  Peter Chang-Lin Wu

Designer： David Ching Chi Chu ,  Peter Chang-Lin Wu