公开(公告)号：US08332659B2

公开(公告)日：2012-12-11

申请号：US12181352

申请日：2008-07-29

Applicant: Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson

Inventor： Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson

IPC: G06F21/00

CPC classification number: G06F21/75 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: Method and apparatus and associated method of detecting microchip tampering may include a conductive element in electrical communication with multiple sensors for verifying that signal degradation occurs at an expected region of the conductive element. A detected variance from the expected region may automatically trigger an action for impeding an integrated circuit exploitation process.

Abstract translation: 用于检测微芯片篡改的方法和装置以及相关联的方法可以包括与多个传感器电连通的导电元件，用于验证在导电元件的预期区域处发生信号劣化。 检测到的与预期区域的差异可以自动地触发阻止集成电路开发过程的动作。

公开(公告)号：US20120306088A1

公开(公告)日：2012-12-06

申请号：US13151672

申请日：2011-06-02

Applicant: Gerald K. BARTLEY ,  Charles L. JOHNSON ,  John E. KELLY, III ,  David R. MOTSCHMAN

Inventor： Gerald K. BARTLEY ,  Charles L. JOHNSON ,  John E. KELLY, III ,  David R. MOTSCHMAN

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L29/0657 ,  H01L23/3677 ,  H01L23/4275 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: The exemplary embodiments of the present invention provide a method and apparatus for enhancing the cooling of a chip stack of semiconductor chips. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes creating a cavity in a second side of the first chip between the connectors and filling the cavity with a thermal material. The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes wherein portions of a second side of the first chip between the connectors is removed to provide a cavity in which a thermal material is placed.

Abstract translation: 本发明的示例性实施例提供了一种用于增强半导体芯片的芯片堆叠的冷却的方法和装置。 该方法包括在第一侧上创建具有电路的第一芯片，并通过连接器网格将第二芯片电连接并机械耦合到第一芯片。 该方法还包括在连接器之间的第一芯片的第二侧中形成空腔，并用热材料填充空腔。 具有增强的冷却装置的半导体芯片的芯片堆叠包括具有第一侧上的电路的第一芯片和通过连接器格栅电和机械地耦合到第一芯片的第二芯片。 该装置还包括：其中，连接器之间的第一芯片的第二侧的部分被去除以提供放置热材料的空腔。

公开(公告)号：US20120187570A1

公开(公告)日：2012-07-26

申请号：US13422606

申请日：2012-03-16

Applicant: Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

Inventor： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.

公开(公告)号：US08172140B2

公开(公告)日：2012-05-08

申请号：US12181401

申请日：2008-07-29

Applicant: Gerald K Bartley ,  Darryl J. Becker ,  Todd A. Christensen ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

Inventor： Gerald K Bartley ,  Darryl J. Becker ,  Todd A. Christensen ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

IPC: G06K7/08

CPC classification number: G06F21/87

Abstract: A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation.

Abstract translation: 一种方法和装置包括掺杂在微芯片内的导电材料，其在离子存在下累积可检测的电荷。 这样的离子可能由聚焦离子束或其他不受欢迎的技术开发而产生。 感测嵌入的掺杂材料中的电荷积累的电路可以启动旨在击败篡改操作的防御动作。

公开(公告)号：US07996641B2

公开(公告)日：2011-08-09

申请号：US12053231

申请日：2008-03-21

Applicant: Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

Inventor： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

IPC: G06F13/00

CPC classification number: G06F13/4243

Abstract: A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.

Abstract translation: 提供了一种用于高容量存储器子系统中的集线器的设计结构，其中存储器模块布置在一个或多个集群中，每个集群都附接到相应的集线器，而集线器又连接到存储器控制器。 在集群内，数据被交织，以便每个数据访问命令访问集群的所有模块。 集线器以较低的总线频率与存储器模块通信，但是在多个模块之间分配数据使集群能够保持存储器 - 控制器到集线器总线的复合数据速率。 优选地，存储器系统采用具有双模操作的缓冲存储器芯片，其中之一支持数据被交错的集群配置，并且通信总线以减小的总线宽度和/或减少的总线频率进行操作以匹配交织级别。

公开(公告)号：US07884625B2

公开(公告)日：2011-02-08

申请号：US12181365

申请日：2008-07-29

Applicant: Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson

Inventor： Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson

IPC: G01R27/26

CPC classification number: H01L23/576 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/3011 ,  H01L2224/0401

Abstract: Apparatus, method and program product may detect an attempt to tamper with a microchip by detecting an unacceptable alteration in a measured capacitance associated with capacitance structures proximate the backside of a microchip. The capacitance structures typically include metallic shapes and may connect using through-silicon vias to active sensing circuitry within the microchip. In response to the sensed change, a shutdown, spoofing, self-destruct or other defensive action may be initiated to protect security sensitive circuitry of the microchip.

Abstract translation: 装置，方法和程序产品可以通过检测与微芯片的背面附近的电容结构相关联的测量电容中的不可接受的改变来检测试图篡改微芯片。 电容结构通常包括金属形状，并且可以使用硅硅通孔连接到微芯片内的主动感测电路。 响应于感测到的变化，可以启动关机，欺骗，自毁或其他防御动作以保护微芯片的安全敏感电路。

公开(公告)号：US07791978B2

公开(公告)日：2010-09-07

申请号：US12024443

申请日：2008-02-01

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  John M. Borkenhagen ,  Philip R. Germann ,  William P Hovis

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  John M. Borkenhagen ,  Philip R. Germann ,  William P Hovis

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C11/4087

Abstract: A design structure embodied in a machine readable medium used in a design process includes random access memory device having an array of individual memory cells arranged into rows and columns, each memory cell having an access device associated therewith. Each row of the array further includes a plurality of N word lines associated therewith, with a wherein N corresponds to a number of independently accessible partitions of the array, wherein each access device in a given row is coupled to only one of the N word lines of the row. Logic in signal communication with the array receives a plurality of row address bits and determine, for a requested row identified by the row address bits, which of the N partitions within the requested row are to be accessed, such that access devices within a selected row, but not within a partition to be accessed, are not activated.

Abstract translation: 体现在设计过程中使用的机器可读介质中的设计结构包括具有布置成行和列的各个存储单元的阵列的随机存取存储器件，每个存储单元具有与其相关联的访问设备。 阵列的每行还包括与其相关联的多个N字线，其中N对应于阵列的独立可访问分区的数量，其中给定行中的每个访问设备仅耦合到N个字线中的一个 的行。 与阵列的信号通信中的逻辑接收多个行地址位，并且对于由行地址位标识的请求行，确定要请求的行内的N个分区中的哪一个被访问，使得所选行中的访问设备 ，但不在要访问的分区内，则不会被激活。

公开(公告)号：US20100185410A1

公开(公告)日：2010-07-22

申请号：US12354958

申请日：2009-01-16

Applicant: GERALD K. BARTLEY ,  CHARLES L. JOHNSON ,  MARK M. THORNTON ,  PATRICK R. VAREKAMP

Inventor： GERALD K. BARTLEY ,  CHARLES L. JOHNSON ,  MARK M. THORNTON ,  PATRICK R. VAREKAMP

IPC: G06F19/00 ,  H01L21/66 ,  H01L23/58

CPC classification number: G06F19/00 ,  H01L22/14 ,  H01L22/20 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) chip is fabricated from components that have been cut out of a two-dimensional (2D) chip to create the layers of the 3D chip. By testing the 2D chip first, the layers of the 3D chip have been pre-tested, thus reducing testing and production costs.

Abstract translation: 三维（3D）芯片由已经从二维（2D）芯片切出的部件制造以产生3D芯片的层。 首先通过测试2D芯片，3D芯片的层已经过预先测试，从而降低了测试和生产成本。

公开(公告)号：US20100026506A1

公开(公告)日：2010-02-04

申请号：US12181342

申请日：2008-07-29

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G08B21/00

CPC classification number: G06F21/86 ,  H01L23/576 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/16251 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An apparatus and method detect microchip tampering by including a capacitance circuit that comprises a protective cover. Dielectric material may be sandwiched between the cover and a backside metal layer, which may be proximate a protected surface of the microchip. Changes in the capacitance of the above circuit caused by alteration of the cover or other component of the capacitance circuit may be sensed and prompt defensive action.

Abstract translation: 一种装置和方法，通过包括包括保护盖的电容电路来检测微芯片篡改。 电介质材料可以夹在盖子和背面金属层之间，背面金属层可以靠近微芯片的受保护表面。 可以感测到由电容电路的盖或其他部件的改变引起的上述电路的电容的变化，并且具有迅速的防御作用。

公开(公告)号：US20100026326A1

公开(公告)日：2010-02-04

申请号：US12181387

申请日：2008-07-29

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  John E. Sheets, II

IPC: G01R27/08

CPC classification number: G06F21/755 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis.

Abstract translation: 一种方法，程序产品和装置包括位于安全敏感的微芯片电路附近的电阻结构。 可以检测抵抗结构的位置，构成或布置的变化，并启动防止逆向工程或其他开发工作的动作。 电阻结构可以被自动和选择性地指定用于监测。 一些电阻结构可能具有不同的电阻率。 感测的电阻可以与期望的电阻，比率或其他电阻相关值进行比较。 结构可能与假结构混合，并且可以相对于彼此重叠或以其它方式布置，以进一步使不受欢迎的分析复杂化。