公开(公告)号：US09495498B2

公开(公告)日：2016-11-15

申请号：US13618600

申请日：2012-09-14

Applicant: Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

Inventor： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel ,  Patrick Ronald Varekamp

IPC: H01L25/00 ,  G06F17/50 ,  H01L25/065

CPC classification number: G06F17/5068 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers.

Abstract translation: 一种装置，程序产品和方法有助于在多层半导体堆叠中结合通用的标准化层间互连的多层电路装置的设计，以便于布置在半导体管芯堆叠上的功能单元之间的互连和通信。 多层半导体堆叠中的每个电路层需要包括布置在基本上相同的地形位置处的层间界面区域，使得当将这样的电路层设置在其上的半导体管芯堆叠在一起时，电气 布置在每个半导体管芯内的导体彼此对准以提供相对于各个电路层垂直或横向取向的层间总线。

公开(公告)号：US08823090B2

公开(公告)日：2014-09-02

申请号：US13029490

申请日：2011-02-17

Applicant: Gerald K Bartley ,  Darryl J Becker ,  Philip R Germann ,  Andrew B Maki ,  John E Sheets, II

Inventor： Gerald K Bartley ,  Darryl J Becker ,  Philip R Germann ,  Andrew B Maki ,  John E Sheets, II

IPC: H01L29/772

CPC classification number: H01L29/7827 ,  H01L21/26586 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66666 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/00

Abstract: A field-effect transistor has a gate, a source, and a drain. The gate has a via extending through a semiconductor chip substrate from one surface to an opposite surface of the semiconductor chip substrate. The source has a first toroid of ion dopants implanted in the semiconductor chip substrate surrounding one end of the via on the one surface of the semiconductor chip substrate. The drain has a second toroid of ion dopants implanted in the semiconductor chip substrate surrounding an opposite end of the via on the opposite surface of the semiconductor chip substrate.

Abstract translation: 场效应晶体管具有栅极，源极和漏极。 栅极具有从半导体芯片基板的一个表面延伸穿过半导体芯片基板的相对表面的通孔。 源极在半导体芯片衬底的一个表面上具有注入在半导体芯片衬底中的第一环状的离子掺杂剂，该半导体芯片衬底围绕通孔的一端。 漏极具有注入在半导体芯片衬底中的第二环形离子掺杂剂，该环状氧化物围绕半导体芯片衬底的相对表面上的通孔的相对端。

公开(公告)号：US20130277798A1

公开(公告)日：2013-10-24

申请号：US13449480

申请日：2012-04-18

Applicant: Gerald K. Bartley ,  Philip R. Germann ,  John E. Sheets, II

Inventor： Gerald K. Bartley ,  Philip R. Germann ,  John E. Sheets, II

IPC: H01L29/02 ,  H01L21/02

CPC classification number: H01L29/945 ,  H01L29/66181

Abstract: A method and structures are provided for implementing semiconductor signal-capable capacitors with deep trench and Through-Silicon-Via (TSV) technologies. A deep trench N-well structure is formed and an implant is provided in the deep trench N-well structure with a TSV formed in a semiconductor chip. At least one angled implant is created around the TSV in a semiconductor chip. The TSV is surrounded with a dielectric layer and filled with a conducting material which forms one electrode of the capacitor. A connection is made to one implant forming a second electrode to the capacitor.

Abstract translation: 提供了一种用于实现具有深沟槽和透硅（Via-Silicon-Via，TSV）技术的具有半导体信号能力的电容器的方法和结构。 形成深沟槽N阱结构，并且在深沟槽N阱结构中提供植入物，其中TSV形成在半导体芯片中。 在半导体芯片中的TSV周围形成至少一个成角度的植入物。 TSV被介电层包围并填充有形成电容器的一个电极的导电材料。 连接到形成到电容器的第二电极的一个注入件。

公开(公告)号：US08445918B2

公开(公告)日：2013-05-21

申请号：US12855854

申请日：2010-08-13

Applicant: Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

Inventor： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

IPC: H01L31/0312

CPC classification number: H01L23/50 ,  G06F17/5068 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/0612 ,  H01L2224/06181 ,  H01L2224/06519 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A circuit arrangement and method in one aspect utilize thermal-only through vias, extending between the opposing faces of stacked semiconductor dies, to increase the thermal conductivity of a multi-layer semiconductor stack. The thermal vias are provided in addition to data-carrying through vias, which communicate data signals between circuit layers, and power-carrying through vias, which are coupled to a power distribution network for the circuit layers, such that the thermal conductivity is increased above that which may be provided by the data-carrying and power-carrying through vias in the stack. A circuit arrangement and method in another aspect organize the circuit layers in a multi-layer semiconductor stack based upon current density so as to reduce power distribution losses in the stack.

Abstract translation: 一个方面的电路装置和方法利用仅在通孔之间通过在堆叠的半导体管芯的相对表面之间延伸的热，以增加多层半导体堆叠的导热性。 除了通过通孔之类的数据传送之外，提供了热通孔，该通路通过电路层之间传送数据信号，并通过通孔进行通电，通孔与耦合到电路层的配电网络，使得热导率增加到 可以通过堆叠中的通孔的数据携带和供电来提供。 另一方面的电路装置和方法基于电流密度组织多层半导体堆叠中的电路层，以便减少堆叠中的功率分配损失。

公开(公告)号：US20130011968A1

公开(公告)日：2013-01-10

申请号：US13618656

申请日：2012-09-14

Applicant: Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

Inventor： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

IPC: H01L21/50

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.

Abstract translation: 电路布置和方法利用混合键合技术，其将晶片 - 晶片接合工艺与芯片芯片和/或晶片 - 晶片接合工艺组合以形成多层半导体堆叠，例如通过将由一个或多个子组件 使用芯片芯片和/或芯片 - 晶片接合工艺与其它子组件和/或芯片一起进行晶片 - 晶片接合。 通过这样做，可以利用芯片芯片和芯片 - 晶片结合技术的优点来利用诸如更高互连密度的晶片 - 晶片接合技术的优点，例如混合和匹配具有不同尺寸，长宽比的芯片和 功能。

公开(公告)号：US20120098140A1

公开(公告)日：2012-04-26

申请号：US12911879

申请日：2010-10-26

Applicant: Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

Inventor： Gerald K. Bartley ,  Russell Dean Hoover ,  Charles Luther Johnson ,  Steven Paul VanderWiel

IPC: H01L23/538 ,  H01L21/50

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions.

Abstract translation: 电路布置和方法利用混合键合技术，其将晶片 - 晶片接合工艺与芯片芯片和/或晶片 - 晶片接合工艺组合以形成多层半导体堆叠，例如通过将由一个或多个子组件 使用芯片芯片和/或芯片 - 晶片接合工艺与其它子组件和/或芯片一起进行晶片 - 晶片接合。 通过这样做，可以利用芯片芯片和芯片 - 晶片结合技术的优点来利用诸如更高互连密度的晶片 - 晶片接合技术的优点，例如混合和匹配具有不同尺寸，长宽比的芯片和 功能。

公开(公告)号：US20120038057A1

公开(公告)日：2012-02-16

申请号：US12855854

申请日：2010-08-13

Applicant: Gerald K. Bartley ,  Russell D. Hoover ,  Charles L. Johnson ,  Steven P. VanderWiel

Inventor： Gerald K. Bartley ,  Russell D. Hoover ,  Charles L. Johnson ,  Steven P. VanderWiel

IPC: H01L23/538 ,  G06F17/50 ,  H01L21/50

CPC classification number: H01L23/50 ,  G06F17/5068 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/0612 ,  H01L2224/06181 ,  H01L2224/06519 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A circuit arrangement and method in one aspect utilize thermal-only through vias, extending between the opposing faces of stacked semiconductor dies, to increase the thermal conductivity of a multi-layer semiconductor stack. The thermal vias are provided in addition to data-carrying through vias, which communicate data signals between circuit layers, and power-carrying through vias, which are coupled to a power distribution network for the circuit layers, such that the thermal conductivity is increased above that which may be provided by the data-carrying and power-carrying through vias in the stack. A circuit arrangement and method in another aspect organize the circuit layers in a multi-layer semiconductor stack based upon current density so as to reduce power distribution losses in the stack.

Abstract translation: 一个方面的电路装置和方法利用仅在通孔之间通过在堆叠的半导体管芯的相对表面之间延伸的热，以增加多层半导体堆叠的导热性。 除了通过通孔之类的数据传送之外，提供了热通孔，该通路通过电路层之间传送数据信号，并通过通孔进行通电，通孔与耦合到电路层的配电网络，使得热导率增加到 可以通过堆叠中的通孔的数据携带和供电来提供。 另一方面的电路装置和方法基于电流密度组织多层半导体堆叠中的电路层，以便减少堆叠中的功率分配损失。

公开(公告)号：US08037258B2

公开(公告)日：2011-10-11

申请号：US12053185

申请日：2008-03-21

Applicant: Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

Inventor： Gerald K. Bartley ,  John M. Borkenhagen ,  Philip Raymond Germann

IPC: G06F12/00

CPC classification number: G06F12/0844 ,  G06F12/0607 ,  G06F12/0851

Abstract: A design structure is provided for a dual-mode memory chip supporting a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.

Abstract translation: 提供了一种支持第一操作模式的双模式存储器芯片的设计结构，其中接收的数据访问命令包含芯片选择数据以识别由命令寻址的芯片，并且存储器芯片中的控制逻辑确定该命令是否被寻址到 芯片和第二操作模式，其中所接收的数据访问命令寻址一组多个芯片。 优选地，第一模式支持存储芯片的菊花链配置。 优选地，第二模式支持分层交错存储器子系统，其中每个可寻址的芯片集合被配置为树，命令和写入数据在树下传播，在树的每个后续级别增加的码片数量。

公开(公告)号：US07952478B2

公开(公告)日：2011-05-31

申请号：US12181342

申请日：2008-07-29

Applicant: Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson

Inventor： Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson

IPC: G08B13/00

CPC classification number: G06F21/86 ,  H01L23/576 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/16251 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An apparatus and method detect microchip tampering by including a capacitance circuit that comprises a protective cover. Dielectric material may be sandwiched between the cover and a backside metal layer, which may be proximate a protected surface of the microchip. Changes in the capacitance of the above circuit caused by alteration of the cover or other component of the capacitance circuit may be sensed and prompt defensive action.

Abstract translation: 一种装置和方法，通过包括包括保护盖的电容电路来检测微芯片篡改。 电介质材料可以夹在盖子和背面金属层之间，背面金属层可以靠近微芯片的受保护表面。 可以感测到由电容电路的盖或其他部件的改变引起的上述电路的电容的变化，并且具有迅速的防御作用。

公开(公告)号：US20100031375A1

公开(公告)日：2010-02-04

申请号：US12181352

申请日：2008-07-29

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G06F21/02

CPC classification number: G06F21/75 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: Method and apparatus and associated method of detecting microchip tampering may include a conductive element in electrical communication with multiple sensors for verifying that signal degradation occurs at an expected region of the conductive element. A detected variance from the expected region may automatically trigger an action for impeding an integrated circuit exploitation process.

Abstract translation: 用于检测微芯片篡改的方法和装置以及相关联的方法可以包括与多个传感器电连通的导电元件，用于验证在导电元件的预期区域处发生信号劣化。 检测到的与预期区域的差异可以自动地触发阻止集成电路开发过程的动作。