公开(公告)号：US09003559B2

公开(公告)日：2015-04-07

申请号：US12181357

申请日：2008-07-29

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  Carl-Otto Nilsen

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson ,  Carl-Otto Nilsen

IPC: G06F1/26 ,  G06F11/00 ,  G08B13/00 ,  G08B21/00 ,  G08B29/00 ,  G06F21/87

CPC classification number: G06F21/87

Abstract: Apparatus, method and program product detect an attempt to tamper with a microchip by determining that an electrical path comprising one or more connections and a metal plate attached to the backside of a microchip has become disconnected or otherwise altered. A tampering attempt may also be detected in response to the presence of an electrical path that should not be present, as may result from the microchip being incorrectly reconstituted. Actual and/or deceptive paths may be automatically selected and monitored to further confound a reverse engineering attempt.

Abstract translation: 装置，方法和程序产品通过确定包括一个或多个连接的电路径和连接到微芯片的背面的金属板已经断开或以其他方式改变来检测试图篡改微芯片。 响应于不可能存在的电路径的存在，也可以检测到篡改尝试，这可能是因为微芯片被错误地重新构成。 可以自动选择和监视实际和/或欺骗性路径，以进一步混淆反向工程尝试。

公开(公告)号：US08466024B2

公开(公告)日：2013-06-18

申请号：US12966303

申请日：2010-12-13

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Philip R. Germann ,  Andrew B. Maki ,  John E. Sheets, II

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Philip R. Germann ,  Andrew B. Maki ,  John E. Sheets, II

IPC: H01L21/336

CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823437 ,  H01L23/481 ,  H01L29/785 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2924/014

Abstract: A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower level semiconductor chip and a higher semiconductor chip to control whether a voltage supply on the lower level semiconductor chip is connected to or disconnected from a voltage domain in the upper level semiconductor chip. The TSVG comprises an FET controlled by the lower level chip as a switch.

Abstract translation: 半导体芯片具有选通硅通孔（TSVG）。 可以切换TSVG，使得TSVG可以导通或不导通。 半导体芯片可以在下位半导体芯片和较高半导体芯片之间使用，以控制下位半导体芯片上的电压供应是连接到上级半导体芯片中的电压域还是与其断开。 TSVG包括由下级芯片作为开关控制的FET。

公开(公告)号：US08457920B2

公开(公告)日：2013-06-04

申请号：US12789669

申请日：2010-05-28

Applicant: Benjamin A. Fox ,  Nathaniel J. Gibbs ,  Andrew B. Maki ,  Trevor J. Timpane

Inventor： Benjamin A. Fox ,  Nathaniel J. Gibbs ,  Andrew B. Maki ,  Trevor J. Timpane

IPC: G01R31/28

CPC classification number: H01L22/20 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer comprises a first chip and a second chip, each chip comprising a core, link layer and physical layer. A kerf area physically connects the two chips on the wafer, and a kerf area interconnect selectively couples the link layers of the two chips while the two physical layers are disabled.

Abstract translation: 半导体晶片包括第一芯片和第二芯片，每个芯片包括核心，链路层和物理层。 切口区域物理地连接晶片上的两个芯片，并且切口区域互连选择性地耦合两个芯片的链路层，而两个物理层被禁用。

公开(公告)号：US07940878B2

公开(公告)日：2011-05-10

申请号：US11678256

申请日：2007-02-23

Applicant: Steven J. Baumgartner ,  Timothy C. Buchholtz ,  Andrew D. Davies ,  Thomas W. Liang ,  Andrew B. Maki ,  Thomas Pham ,  Dana M. Woeste ,  Daniel G. Young

Inventor： Steven J. Baumgartner ,  Timothy C. Buchholtz ,  Andrew D. Davies ,  Thomas W. Liang ,  Andrew B. Maki ,  Thomas Pham ,  Dana M. Woeste ,  Daniel G. Young

IPC: H03D3/24 ,  H04L7/00

CPC classification number: H03L7/0812 ,  H04L7/0008

Abstract: A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.

Abstract translation: 锁相环产生对应于源同步输入和输入链路时钟信号的输出。 相位锁定反馈系统接收输入和输入链路时钟信号，并检测输出和输入之间的相位偏差。 相位锁定反馈系统还基于相位偏差来调整调整的时钟信号，从而使相位锁定反馈系统产生输出，使得输出与输入具有稳定的相位关系。 第一机制使得相位锁定反馈系统在出现第一预定义事件时不跟踪输出和输入之间的相位偏差，从而将经调整的时钟信号保持在当前状态。

公开(公告)号：US07701244B2

公开(公告)日：2010-04-20

申请号：US12181367

申请日：2008-07-29

Applicant: Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson ,  John E. Sheets, II

Inventor： Gerald K Bartley ,  Darryl J Becker ,  Paul E Dahlen ,  Philip R Germann ,  Andrew B Maki ,  Mark O Maxson ,  John E. Sheets, II

IPC: H03K19/00

CPC classification number: G06F21/86 ,  G06F21/75 ,  H01L23/57 ,  H01L2224/32225

Abstract: An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected.

Abstract translation: 检测微芯片篡改的集成电路组件和相关联的方法可以包括与导电层电连通的多个连接。 防御性电路可能会阻止微芯片的分析，其中连接不再连接到导电层。 防御性电路可以类似地启动，其中连接不想与导电层电连通的连接是连接的。

公开(公告)号：US07667487B2

公开(公告)日：2010-02-23

申请号：US11971966

申请日：2008-01-10

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: H03K19/173

CPC classification number: G06F1/26

Abstract: A circuit assembly includes a functional chip and a first capacitor. The functional chip includes a first logic island and a second logic island. The first capacitor is configured to be selectively coupled (e.g., at different times) to a first power supply terminal of the first logic island and a second power supply terminal of the second logic island.

Abstract translation: 电路组件包括功能芯片和第一电容器。 功能芯片包括第一逻辑岛和第二逻辑岛。 第一电容器被配置为选择性地耦合（例如，在不同的时间）耦合到第一逻辑岛的第一电源端子和第二逻辑岛的第二电源端子。

公开(公告)号：US20090179669A1

公开(公告)日：2009-07-16

申请号：US11971966

申请日：2008-01-10

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: H03K19/0175 ,  G06F1/26

CPC classification number: G06F1/26

Abstract: A circuit assembly includes a functional chip and a first capacitor. The functional chip includes a first logic island and a second logic island. The first capacitor is configured to be selectively coupled (e.g., at different times) to a first power supply terminal of the first logic island and a second power supply terminal of the second logic island.

Abstract translation: 电路组件包括功能芯片和第一电容器。 功能芯片包括第一逻辑岛和第二逻辑岛。 第一电容器被配置为选择性地耦合（例如，在不同的时间）耦合到第一逻辑岛的第一电源端子和第二逻辑岛的第二电源端子。

公开(公告)号：US20090079060A1

公开(公告)日：2009-03-26

申请号：US11860226

申请日：2007-09-24

Applicant: GERALD K. BARTLEY ,  Darryl L. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： GERALD K. BARTLEY ,  Darryl L. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: H01L23/15 ,  H01L21/98

CPC classification number: H01L21/563 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81365 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2924/0001 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2224/13099

Abstract: A method of making an integrated circuit package includes forming a through hole in an integrated circuit and assembling a die containing the integrated circuit on a carrier so that the die is mechanically and electrically connected to the carrier. Thereafter, an underfill material is dispensed between the die and the carrier via the through hole.

Abstract translation: 制造集成电路封装的方法包括在集成电路中形成通孔并将包含集成电路的管芯组装在载体上，使得管芯机械地和电连接到载体上。 此后，通过通孔将底部填充材料分配在模具和载体之间。

公开(公告)号：US20090058425A1

公开(公告)日：2009-03-05

申请号：US11848652

申请日：2007-08-31

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G01R31/02

CPC classification number: G01R31/2808 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/111 ,  H05K2201/09063

Abstract: An apparatus for testing electrical continuity of a surface mounted (SMT) electrical board includes: a printed wiring board having a first surface and an opposite second surface; a conductive signal line disposed on each of the first and second surfaces of the printed wiring board; an electrical component disposed on and electrically connected to the conductive signal line on the first surface; and a through hole extending through the printed wiring board and the conductive signal line on the second surface of the printed wiring board exposing a surface side of the conductive signal line facing the first surface of the printed wiring board. The through hole is unplated in an inside bore defining the through hole and the through hole allows direct access to the conductive signal line on the first surface to test continuity of the conductive signal line on the first surface connected to the electrical component from the second surface of the printed wiring board.

Abstract translation: 一种用于测试表面安装（SMT）电气板的电气连续性的装置包括：具有第一表面和相对的第二表面的印刷线路板; 布置在所述印刷电路板的所述第一表面和所述第二表面中的每一个上的导电信号线; 设置在第一表面上并电连接到第一表面上的导电信号线的电气部件; 以及延伸穿过印刷线路板的通孔和印刷线路板的第二表面上的导电信号线，其暴露导电信号线的面对印刷线路板的第一表面的表面侧。 在限定通孔的内孔中没有通孔，并且通孔允许直接进入第一表面上的导电信号线，以测试从第二表面连接到电气部件的第一表面上的导电信号线的连续性 的印刷线路板。

公开(公告)号：US07477568B2

公开(公告)日：2009-01-13

申请号：US12034773

申请日：2008-02-21

Applicant: Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

Inventor： Gerald K. Bartley ,  Darryl J. Becker ,  Paul E. Dahlen ,  Philip R. Germann ,  Andrew B. Maki ,  Mark O. Maxson

IPC: G11C8/00

CPC classification number: G11C5/063 ,  G11C7/1048 ,  G11C7/1066

Abstract: A double-data-rate two synchronous dynamic random access (DDR2 ) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core having a common output wherein a high-speed output path and a low-speed output path are coupled together by an output coupling and further coupled to the common output of the memory core.

Abstract translation: 双数据速率两同步动态随机存取（DDR2）存储器电路包括低速输入路径和通过输入耦合耦合到其上的高速输入路径并形成公共输入，公共输入耦合到存储器核心 存储器芯具有公共输出，其中高速输出路径和低速输出路径通过输出耦合耦合在一起并进一步耦合到存储器核心的公共输出端。