公开(公告)号：US06184714B2

公开(公告)日：2001-02-06

申请号：US09030197

申请日：1998-02-25

申请人： Howard C. Kirsch ,  Ena Ku

发明人： Howard C. Kirsch ,  Ena Ku

IPC分类号： H03K1902

CPC分类号： H04L25/0282 ,  H04L5/04 ,  H04L25/0294

摘要： A current mode data communication system is disclosed. The current mode data communication system has a transmitter to simultaneously transmit two digital data bits. The two digital data bits are combined to form a current mode signal. The current mode signal has a first positive current, a second positive current, a first negative current and a first positive current. The current mode signal will be transmitted on a double bit current mode bus. Further the current mode communication system has a receiver coupled to the double bit current mode bus to receive the current mode signal and convert the current mode signal to a unextracted form of the two digital data bits. The output of the receiver is connected to a data extractor circuit extract the two digital data bits for the unextracted form of the two digital data bits.

公开(公告)号：US5739564A

公开(公告)日：1998-04-14

申请号：US460605

申请日：1995-06-01

申请人： Yasunobu Kosa ,  Howard C. Kirsch ,  Thomas F. McNelly ,  Frank Kelsey Baker

发明人： Yasunobu Kosa ,  Howard C. Kirsch ,  Thomas F. McNelly ,  Frank Kelsey Baker

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/265 ,  H01L21/70

CPC分类号： H01L27/11

摘要： A static-random-access memory cell comprising floating node capacitors is disclosed. In one embodiment, the storage nodes acts as the first plates for the floating node capacitors, and a conductive member acts as the second plates for the floating node capacitors. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cell. In another embodiment, a conductive member acts as the second plates of a plurality of memory cells. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cells. Processes for forming the memory cells is also disclosed.

摘要翻译： 公开了一种包括浮动节点电容器的静态随机存取存储器单元。 在一个实施例中，存储节点用作浮动节点电容器的第一板，并且导电构件用作浮动节点电容器的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 在另一个实施例中，导电构件用作多个存储单元的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 还公开了用于形成存储单元的工艺。

公开(公告)号：US5364810A

公开(公告)日：1994-11-15

申请号：US921039

申请日：1992-07-28

申请人： Yasunobu Kosa ,  Howard C. Kirsch

发明人： Yasunobu Kosa ,  Howard C. Kirsch

IPC分类号： H01L27/10 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L29/66666 ,  H01L21/26586 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/6675 ,  H01L29/7827 ,  H01L29/7834 ,  Y10S257/904

摘要： The disclosure includes a vertical field-effect transistor (115) with a laterally recessed channel region (92), a vertical field-effect transistor (116) having a graded diffusion junction (31), a static random access memory cell (110) having a vertical n-channel field-effect transistor (116) and a vertical p-channel field-effect transistor (115) and methods of forming them. In one embodiment, a six-transistor static random access memory cell (110) has two pass transistors (111 and 114), which are planar n-channel field-effect transistors, two latch transistors (113 and 116), which are vertical n-channel field-effect transistors with drain regions having graded diffusion junctions (31), and two load transistors (112 and 115), which are vertical p-channel thin-film field-effect transistors having laterally recessed channel regions (92).

摘要翻译： 本公开包括具有横向凹陷沟道区域（92）的垂直场效应晶体管（115），具有渐变扩散结（31）的垂直场效应晶体管（116），具有梯度扩散结（31）的静态随机存取存储单元（110） 垂直n沟道场效应晶体管（116）和垂直p沟道场效应晶体管（115）及其形成方法。 在一个实施例中，六晶体管静态随机存取存储单元（110）具有平面n沟道场效应晶体管的两个通过晶体管（111和114），两个垂直n的晶体管（113和116） 具有分级扩散结（31）的漏极区的沟道场效应晶体管和具有侧向凹陷沟道区（92）的垂直p沟道薄膜场效应晶体管的两个负载晶体管（112和115）。

公开(公告)号：US5095347A

公开(公告)日：1992-03-10

申请号：US561385

申请日：1990-08-01

申请人： Howard C. Kirsch

发明人： Howard C. Kirsch

IPC分类号： H01L21/8244 ,  H01L27/06 ,  H01L27/11

CPC分类号： H01L27/0688 ,  H01L27/1108 ,  Y10S257/903

摘要： A plural transistor structure uses shared electrodes to improve the degree of integration circuits such as SRAMs. The degree of integration is improved by forming a gate of a first transistor from a current electrode, such as a drain of a second transistor with the same region of semiconductor material. Furthermore, a gate of the second transistor can be formed from a drain of the first transistor with the same region of material which dramatically reduces the size of a memory cell latch.

摘要翻译： 多晶体管结构使用共享电极来提高诸如SRAM之类的集成电路的程度。 通过从具有相同半导体材料区域的第二晶体管的漏极形成第一晶体管的栅极来改善积分度。 此外，第二晶体管的栅极可以由具有相同材料区域的第一晶体管的漏极形成，这显着地减小了存储器单元锁存器的尺寸。

公开(公告)号：US4583157A

公开(公告)日：1986-04-15

申请号：US699794

申请日：1985-02-08

申请人： Howard C. Kirsch ,  James H. Stefany

发明人： Howard C. Kirsch ,  James H. Stefany

IPC分类号： G11C11/407 ,  G05F1/62 ,  G11C5/14 ,  G11C8/08 ,  H02M3/07 ,  H03K17/06 ,  H03K19/094 ,  H02M3/18 ,  H03K5/02

CPC分类号： H02M3/07 ,  G05F1/62 ,  G11C5/145 ,  G11C8/08 ,  H02M2001/0022

摘要： An integrated circuit comprises a node that is boosted by one or more boost capacitors depending on the level of the power supply voltage. When the level is below a given threshold, a first booster capacitor is activated. Additional boost capacitors may be provided for activation at still lower thresholds. The boost capacitors are deactivated when the power supply level exceeds the corresponding thresholds. In this manner, a more constant boosted voltage is obtained. This provides for an adequate boosted voltage at low power supply levels, while avoiding excessive boost at high power supply voltages that could damage devices. The technique may be used for boosted row conductors in dynamic random access memories, among other applications.

摘要翻译： 集成电路包括根据电源电压的电平由一个或多个升压电容器升压的节点。 当电平低于给定阈值时，第一升压电容器被激活。 可以提供额外的升压电容器用于以更低的阈值激活。 当电源电平超过相应的阈值时，升压电容器将被禁用。 以这种方式，获得更恒定的升压电压。 这提供了在低电源电平下的适当的升压电压，同时避免在可能损坏器件的高电源电压下的过度升压。 该技术可用于动态随机存取存储器中的升压行导体，以及其它应用。

公开(公告)号：US4472644A

公开(公告)日：1984-09-18

申请号：US329586

申请日：1981-12-10

申请人： Howard C. Kirsch

发明人： Howard C. Kirsch

IPC分类号： H03K5/13 ,  H03K5/02 ,  H03K5/135 ,  H03K17/284 ,  H03K17/693

CPC分类号： H03K5/135

摘要： A clock generator circuit (10) receives an input signal PPC.0. and generates a delayed clock output signal PC.0.. The circuit (10) is set to an initial condition by a precharge signal PC.0.R prior to a transition of the input signal PPC.0.. A time delay signal is produced at a node (26) by operation of transistors (18, 28). The transition of the input signal PPC.0. produces a bootstrapped voltage at a capacitor (68). The delay signal activates a transistor (80) to couple the bootstrapped voltage to the gate terminal of an output transistor (88). The gate terminal of the output transistor (88) is driven directly from a low voltage state to a boosted high voltage state. This causes the output signal PC.0. to be driven from an initial low voltage state to the power supply voltage V.sub.cc without intervening steps. The output transistors (88, 90) of circuit (10) are never activated at the same time, thereby preventing any current spike from being propagated through the circuit (10).

摘要翻译： 时钟发生器电路（10）接收输入信号PPCO并产生延迟的时钟输出信号PCO。 电路（10）在输入信号PPCO的转换之前由预充电信号PCOR设定为初始状态。 通过晶体管（18,28）的操作在节点（26）处产生时间延迟信号。 输入信号PPCO的转换在电容器（68）产生自举电压。 延迟信号激活晶体管（80）以将自举电压耦合到输出晶体管（88）的栅极端子。 输出晶体管（88）的栅极端子直接从低电压状态驱动到升压高电压状态。 这使得输出信号PCO从初始低电压状态被驱动到电源电压Vcc，而没有中间步骤。 电路（10）的输出晶体管（88,90）不会同时被激活，从而防止任何电流尖峰传播通过电路（10）。

公开(公告)号：US08921899B2

公开(公告)日：2014-12-30

申请号：US12950797

申请日：2010-11-19

申请人： Werner Juengling ,  Howard C. Kirsch

发明人： Werner Juengling ,  Howard C. Kirsch

IPC分类号： H01L27/118 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L27/108 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/7855

摘要： A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.

摘要翻译： 提供一种半导体器件，其包括在第一沟槽中形成有鳍状物的第一侧壁上的第一栅极和第二栅极的鳍片，其中第一栅极形成在第二栅极之上。 该器件包括在第二沟槽中形成在鳍片的第二侧壁上的第三栅极和第四栅极，其中第三栅极形成在第四栅极之上。 还包括制造和操作设备的方法。 一种操作方法可以包括偏置第一栅极和第四栅极以产生穿过散热片的电流路径。

公开(公告)号：US08598912B2

公开(公告)日：2013-12-03

申请号：US12815176

申请日：2010-06-14

申请人： J. Wayne Thompson ,  Howard C. Kirsch ,  Charles L. Ingalls

发明人： J. Wayne Thompson ,  Howard C. Kirsch ,  Charles L. Ingalls

IPC分类号： G01R19/00

CPC分类号： G11C7/12 ,  G11C7/06 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

摘要： Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored.

公开(公告)号：US20120205719A1

公开(公告)日：2012-08-16

申请号：US13455956

申请日：2012-04-25

申请人： Werner Juengling ,  Howard C. Kirsch

发明人： Werner Juengling ,  Howard C. Kirsch

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L21/283

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10891 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/7855

摘要： A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.

公开(公告)号：US08149619B2

公开(公告)日：2012-04-03

申请号：US13026052

申请日：2011-02-11

申请人： Howard C. Kirsch ,  Charles Ingalls ,  Werner Juengling

发明人： Howard C. Kirsch ,  Charles Ingalls ,  Werner Juengling

IPC分类号： G11C14/00

CPC分类号： G11C14/0018 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

摘要： A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.

摘要翻译： 提供一种存储器阵列，其包括具有共享晶体管的源极，漏极和沟道的两个有源栅极的晶体管。 有源栅极中的一个可以耦合到诸如DRAM单元的存储器单元的易失性存储器部分，并且另一有源栅极可以耦合到非易失性存储器部分，例如电荷存储节点，例如 SONOS细胞。 提供了操作存储器阵列的方法，其包括将数据从易失性存储器部分传送到非易失性存储器部分，将数据从非易失性存储器部分传送到易失性存储器部分，以及擦除非易失性存储器部分的非易失性存储器部分 行的存储单元。