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    Programmable spatial array for matrix decomposition
    72.
    发明授权
    Programmable spatial array for matrix decomposition 有权

    公开(公告)号：US12235793B2

    公开(公告)日：2025-02-25

    申请号：US18017077

    申请日：2020-09-25

    Applicant: Intel Corporation

    Inventor： Long Jiang ,  Xu Zhang ,  Hong Cheng

    IPC: G06F15/80 ,  G06F17/16

    Abstract: Programmable spatial array processing circuitry may be programmable to perform multiple different types of matrix decompositions. The programmable spatial array processing circuitry may include an array of processing elements. When programmed with a first instructions, the array performs a first type of matrix decomposition. When programmed with second instructions, the array performs a second type of matrix decomposition. Individual processing elements of the programmable spatial array processing circuitry may avoid having individual instruction memories. Instead, there may be an instruction memory that provides a portion of the first instructions or a portion of the second instructions sequentially to one processing element of a row of processing elements to sequentially propagate to other processing elements of the row of processing elements.

    APPARATUS, SYSTEM, AND METHOD OF CURRENT CONSUMPTION ADJUSTMENT
    74.
    发明申请
    APPARATUS, SYSTEM, AND METHOD OF CURRENT CONSUMPTION ADJUSTMENT 有权

    公开(公告)号：US20250062610A1

    公开(公告)日：2025-02-20

    申请号：US18399290

    申请日：2023-12-28

    Applicant: INTEL CORPORATION

    Inventor： Harel Aronheim ,  Dmitry Felsenstein ,  Ariel Wolf ,  Eran Amir ,  Ofir Klein ,  Yazan Alwilly ,  Sergey Sofer ,  Sagi Belizowski

    IPC: H02J1/14

    Abstract: For example, a current consumption adjuster may be configured to adjust a current consumption from a power supply of an integrated circuit. For example, the current consumption adjuster may include a controllable load circuitry to controllably apply one or more loads to the power supply of the integrated circuit. For example, the current consumption adjuster may include a controller configured to identify a current consumption event including a transition of a current consumption of the integrated circuit from the power supply. For example, the controller may be configured to control activation of the controllable load circuitry to apply an event-based load to the power supply, for example, based on the current consumption event.

    DYNAMIC QUANTIZATION AND MEMORY MANAGEMENT OF KEY-VALUE CACHE FOR SERVING LARGE LANGUAGE MODELS
    75.
    发明申请
    DYNAMIC QUANTIZATION AND MEMORY MANAGEMENT OF KEY-VALUE CACHE FOR SERVING LARGE LANGUAGE MODELS 有权

    公开(公告)号：US20250061316A1

    公开(公告)日：2025-02-20

    申请号：US18934700

    申请日：2024-11-01

    Applicant: Intel Corporation

    Inventor： Sameh Gobriel ,  Nilesh Jain ,  Vui Seng Chua ,  Juan Pablo Munoz ,  Gopi Krishna Jha

    IPC: G06N3/0495 ,  G06N3/082

    Abstract: Key-value (KV) cache paging schemes can improve memory management for KV caches by storing a KV cache page having key tensors and value tensors for a fixed number of tokens in a fixed-sized block in the KV cache of a worker. To further improve memory management, the schemes can be modified to implement dynamic variable quantization. Quantization level of a KV cache page can be set based on a runtime importance score of the KV cache page. In addition, the quantization level of the KV cache page can be set based on the system load. The end result is a scheme that can achieve a high compression ratio of KV cache pages in the KV cache. Fitting more KV cache pages in the KV cache can lead to higher inference throughput, higher system-level user capacity, and higher end-to-end service availability.

    Self-aligned gate endcap (SAGE) architectures with vertical sidewalls
    77.
    发明授权
    Self-aligned gate endcap (SAGE) architectures with vertical sidewalls 有权

    公开(公告)号：US12230714B2

    公开(公告)日：2025-02-18

    申请号：US18622615

    申请日：2024-03-29

    Applicant: Intel Corporation

    Inventor： Ritesh K. Das ,  Kiran Chikkadi ,  Ryan Pearce

    IPC: H01L29/78 ,  H01L29/49 ,  H01L21/02

    Abstract: Self-aligned gate endcap (SAGE) architectures with vertical sidewalls, and methods of fabricating self-aligned gate endcap (SAGE) architectures with vertical sidewalls, are described. In an example, an integrated circuit structure includes a semiconductor fin having sidewalls along a length of the semiconductor fin, each sidewall tapering outwardly from a top of the semiconductor fin toward a bottom of the semiconductor fin. A gate endcap isolation structure is spaced apart from the semiconductor fin and has a length parallel with the length of the semiconductor fin. The gate endcap isolation structure has a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin.

    Embedded die on interposer packages
    78.
    发明授权
    Embedded die on interposer packages 有权

    公开(公告)号：US12230582B2

    公开(公告)日：2025-02-18

    申请号：US18368929

    申请日：2023-09-15

    Applicant: Intel Corporation

    Inventor： John S. Guzek

    IPC: H01L23/538 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L25/07

    Abstract: Integrated circuit (IC) packages having a through-via interposer with an embedded die, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC package may include a through-via interposer with an embedded die, the through-via connections having front to back conductivity. In some embodiments, a die may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the embedded die. In some embodiments, a second IC package in a package-on-package (PoP) arrangement may be disposed on the back side of an IC package having a through-via interposer with an embedded die and may be electrically coupled to the conductive vias.

    Self-assembled guided hole and via patterning over grating
    79.
    发明授权
    Self-assembled guided hole and via patterning over grating 有权

    公开(公告)号：US12230536B1

    公开(公告)日：2025-02-18

    申请号：US17559490

    申请日：2021-12-22

    Applicant: Intel Corporation

    Inventor： Florian Gstrein ,  Eungnak Han ,  Manish Chandhok ,  Gurpreet Singh

    IPC: H01L21/768 ,  H01L23/522

    Abstract: Described herein are IC devices include vias deposited in a regular array, e.g., a hexagonal array, and processes for depositing vias in a regular array. The process includes depositing a guiding pattern over a metal grating, depositing a diblock copolymer over the guiding pattern, and causing the diblock copolymer to self-assemble such one polymer forms an array of cylinders over metal portions of the metal grating. The polymer layer can be converted into a hard mask layer, with one hard mask material forming the cylinders, and a different hard mask material surrounding the cylinders. A cylinder can be selectively etched, and a via material deposited in the cylindrical hole to form a via.

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