公开(公告)号：US20050141318A1

公开(公告)日：2005-06-30

申请号：US10976384

申请日：2004-10-29

申请人： Jin-Yub Lee

发明人： Jin-Yub Lee

IPC分类号： G06F12/06 ,  G06F12/00 ,  G11C5/00 ,  G11C7/02 ,  G11C8/12 ,  H01L23/48 ,  H01L25/04 ,  H01L25/18 ,  H01L27/10

CPC分类号： G11C8/12

摘要： A dual-chip package is disclosed which includes at least two memory chips each of which may contain buffer and flash memories having different address systems from each other. Each memory chip may include a register for storing first and second flag signals each indicative of selections of corresponding memory chips, a comparator circuit for comparing the first and second flag signals in the register with a reference signal to generate a flash access signal and a buffer access signal, and a controller for controlling the buffer memory and the flash memory in response to the flash access signal and the buffer access signal.

摘要翻译： 公开了一种双芯片封装，其包括至少两个存储器芯片，每个存储器芯片可以包含彼此具有不同地址系统的缓冲器和闪速存储器。 每个存储器芯片可以包括用于存储每个指示对应存储器芯片的选择的第一和第二标志信号的寄存器，用于将寄存器中的第一和第二标志信号与参考信号进行比较的比较器电路，以产生闪存访问信号和缓冲器 访问信号，以及用于响应于闪存访问信号和缓冲器访问信号来控制缓冲存储器和闪存的控制器。

公开(公告)号：US20050141273A1

公开(公告)日：2005-06-30

申请号：US10957166

申请日：2004-09-30

申请人： Min-Gun Park ,  Jin-Yub Lee

发明人： Min-Gun Park ,  Jin-Yub Lee

IPC分类号： G06F12/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08

CPC分类号： G11C16/08

摘要： A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a buffer memory, a random data input/output circuit, and a control circuit. The random data input/output circuit receives data in units of sectors from the buffer memory or outputs the data in units of sectors to the buffer memory. The control circuit controls the order and the number of times of inputting/outputting data between the buffer memory and the random data input/output circuit.

摘要翻译： 一种能够以扇区为单位随机输入/输出数据的闪存系统。 闪存系统包括闪存（单元阵列），缓冲存储器，随机数据输入/输出电路和控制电路。 随机数据输入/输出电路以缓冲存储器的扇区为单位接收数据，或以扇区为单位将数据输出到缓冲存储器。 控制电路控制在缓冲存储器和随机数据输入/输出电路之间输入/输出数据的次序和次数。

公开(公告)号：US20050135145A1

公开(公告)日：2005-06-23

申请号：US10957382

申请日：2004-09-30

申请人： You-Sang Lee ,  Jin-Yub Lee

发明人： You-Sang Lee ,  Jin-Yub Lee

IPC分类号： G11C16/02 ,  G11C8/18 ,  G11C11/00 ,  G11C16/32

CPC分类号： G11C16/32 ,  G11C8/18

摘要： A flash memory device includes a flash memory cell array, and an interface circuit, which receives a command and addresses sequentially in synchronization to an external system clock after a predetermined first latency is elapsed from when a chip enable signal is activated, in a read operation, in a program operation, and in an erase operation. The interface circuit receives the command in response to activation of an invoke signal. Therefore, since the flash memory device does not require CLE (Command Latch Enable) signals, ALE (Address Latch Enable) signals, RE (Read Enable) signals and WE (Write Enable) signals, internal circuits of the flash memory device can be simply controlled, thereby reducing a probability of skew generation in chips, improving performance, and decreasing the number of required pins.

摘要翻译： 闪速存储器件包括闪速存储单元阵列和接口电路，该接口电路在读取操作中从启动芯片使能信号起经过预定​​的第一等待时间之后，以与外部系统时钟同步的顺序接收命令和寻址 ，在编程操作中，以及擦除操作。 接口电路响应于调用信号的激活而接收命令。 因此，由于闪存器件不需要CLE（命令锁存使能）信号，ALE（地址锁存使能）信号，RE（读使能）信号和WE（写使能）信号，闪存器件的内部电路可以简单 从而降低了芯片中产生偏斜的可能性，提高了性能，并减少了所需引脚的数量。

公开(公告)号：US20050021918A1

公开(公告)日：2005-01-27

申请号：US10883950

申请日：2004-07-02

申请人： Sang-Won Hwang ,  Jin-Yub Lee

发明人： Sang-Won Hwang ,  Jin-Yub Lee

IPC分类号： G06F12/16 ,  G06F12/14 ,  G11C16/22

CPC分类号： G06F12/1433 ,  G11C16/22

摘要： Methods of controlling a memory system having a non-volatile memory and a volatile memory are provided in which data is received that is to be stored in the non-volatile memory, the received data is temporarily stored in the volatile memory, the temporarily stored data is stored in the non-volatile memory, an address designating a region of the volatile memory as a locked region is received, an input address is received, and it is determined whether the input address corresponds to the locked region. Operation of the non-volatile and volatile memories may also be controlled such that write operations are not performed to the volatile memory if it is determined that the input address corresponds to the locked region.

摘要翻译： 提供了控制具有非易失性存储器和易失性存储器的存储器系统的方法，其中接收要存储在非易失性存储器中的数据，所接收的数据被临时存储在易失性存储器中，临时存储的数据 存储在非易失性存储器中，接收指定易失性存储器的区域作为锁定区域的地址，接收输入地址，并且确定输入地址是否对应于锁定区域。 也可以控制非易失性和易失性存储器的操作，使得如果确定输入地址对应于锁定区域，则不对易失性存储器执行写入操作。

公开(公告)号：US07949819B2

公开(公告)日：2011-05-24

申请号：US11978582

申请日：2007-10-30

申请人： Sang-chul Kang ,  Jin-yub Lee

发明人： Sang-chul Kang ,  Jin-yub Lee

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34

CPC分类号： G11C16/08 ,  G11C16/20

摘要： According to an example embodiment, a method of changing a block size in a flash memory device having a multi-plane scheme may include decoding an external input address and changing the block size of the flash memory device from a first block size to a second block size. The external input address may be decoded into a block address and a page address. The block size of the flash memory device may be changed from the first block size to the second block size by shifting at least one bit of the block address to the page address or shifting at least one bit of the page address to the block address.

摘要翻译： 根据示例实施例，一种改变具有多平面方案的快闪存储器件中的块大小的方法可以包括解码外部输入地址并将闪存器件的块大小从第一块大小改变为第二块 尺寸。 外部输入地址可以被解码为块地址和页地址。 通过将块地址的至少一位移位到页地址或将页地址的至少一位移位到块地址，可以将闪速存储器件的块大小从第一块大小改变为第二块大小。

公开(公告)号：US07835193B2

公开(公告)日：2010-11-16

申请号：US12109721

申请日：2008-04-25

申请人： Jin-Yub Lee

发明人： Jin-Yub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/12

摘要： A flash memory device includes a cell array and a voltage supplying and selecting portion. The cell array includes multiple word lines, and the voltage supplying and selecting portion is configured to generate at least two different voltages to be supplied to the word lines of the cell array during an erase operation.

摘要翻译： 闪存器件包括电池阵列和电压供应和选择部分。 单元阵列包括多个字线，并且电压提供和选择部分被配置为在擦除操作期间产生要提供给单元阵列的字线的至少两个不同的电压。

公开(公告)号：US07773415B2

公开(公告)日：2010-08-10

申请号：US12292741

申请日：2008-11-25

申请人： Dae-Sik Park ,  Jin-Yub Lee

发明人： Dae-Sik Park ,  Jin-Yub Lee

IPC分类号： G11C16/26

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3427

摘要： A flash memory device includes a memory block including word lines arranged between a first selection line and a second selection line, the word lines being divided into a first group and a second group, a control logic configured to determine an activation order of the first and second selection lines and determine first and second read voltages to be supplied to unselected word lines, the control logic determining the activation order according to whether a selected word line belongs to the first group or the second group, and a row selection circuit configured to, during a read operation, drive the unselected word lines with the first and second read voltages, and activate the first and second selection lines, according to the control logic.

摘要翻译： 闪速存储器件包括存储块，其包括布置在第一选择线和第二选择线之间的字线，所述字线被分成第一组和第二组，控制逻辑被配置为确定第一和第二组的激活顺序， 第二选择线，并且确定要提供给未选字线的第一和第二读取电压，所述控制逻辑根据所选择的字线是否属于所述第一组或所述第二组来确定所述激活顺序;以及行选择电路， 在读取操作期间，利用第一和第二读取电压驱动未选择的字线，并根据控制逻辑激活第一和第二选择线。

公开(公告)号：US20100110796A1

公开(公告)日：2010-05-06

申请号：US12609127

申请日：2009-10-30

申请人： Jong-Yeol Park ,  Jin-Yub Lee

发明人： Jong-Yeol Park ,  Jin-Yub Lee

IPC分类号： G11C16/04 ,  G11C16/16

CPC分类号： G11C16/16 ,  G11C16/344

摘要： A method of performing an erase operation in a non-volatile memory device includes a multi-erase operation and a post-erase operation. The multi-erase operation includes multi-erasing multiple memory blocks at the same time using a multi-erase voltage. The post-erase operation includes post-erasing one or more failed memory blocks of the multi-erased memory blocks using a post-erase voltage having sequentially increasing voltage values based on incremental step pulses (ISPs).

摘要翻译： 在非易失性存储器件中执行擦除操作的方法包括多擦除操作和擦除后操作。 多擦除操作包括使用多擦除电压同时多次擦除多个存储器块。 后擦除操作包括使用具有基于增量步进脉冲（ISP）的顺序增加的电压值的擦除后电压来擦除多擦除存储器块的一个或多个失效存储器块。

公开(公告)号：US07684246B2

公开(公告)日：2010-03-23

申请号：US11465323

申请日：2006-08-17

申请人： Yong-Taek Jeong ,  Jin-Yub Lee

发明人： Yong-Taek Jeong ,  Jin-Yub Lee

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C5/145 ,  G11C16/30

摘要： A flash memory device may include a pump, a regulator to control the pump so that an output voltage of the pump is substantially maintained at a target voltage, and a control circuit to control the regulator so that the pump selectively generates a program voltage or an erase voltage. In some embodiments, the output voltage of the pump may be stepped in response to program loop iterations during a program operation, or set to a target voltage during an erase operation.

摘要翻译： 闪存器件可以包括泵，用于控制泵的调节器，使得泵的输出电压基本上保持在目标电压，以及控制电路以控制调节器，使得泵选择性地产生编程电压或 擦除电压。 在一些实施例中，泵的输出电压可以在编程操作期间响应于程序循环迭代而阶梯式，或者在擦除操作期间被设置为目标电压。

公开(公告)号：US20100067312A1

公开(公告)日：2010-03-18

申请号：US12552738

申请日：2009-09-02

申请人： Jin-Yub Lee ,  Su-Chang Jeon

发明人： Jin-Yub Lee ,  Su-Chang Jeon

IPC分类号： G11C7/06 ,  G11C29/00

CPC分类号： G11C29/44 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2029/1208 ,  G11C2029/4402

摘要： A semiconductor memory device includes a memory core and a fail detection circuit. The memory core includes a memory cell array having a plurality of memory cells. The fail detection circuit compares read data with test data to generate a comparison signal representing whether each of the memory cells is failed or not, and accumulates and stores fail information of the memory cells corresponding to a plurality of addresses to output accumulated fail information. The read data are read out from the memory cells in which the test data are written.

摘要翻译： 半导体存储器件包括存储器芯和故障检测电路。 存储器芯包括具有多个存储单元的存储单元阵列。 失败检测电路将读取数据与测试数据进行比较以产生表示每个存储单元是否故障的比较信号，并且累积并存储与多个地址相对应的存储单元的故障信息以输出累积的故障信息。 从写入测试数据的存储单元读出读取的数据。