公开(公告)号：US20080186071A1

公开(公告)日：2008-08-07

申请号：US12060889

申请日：2008-04-02

申请人： Louis C. Hsu ,  Brian L. Ji ,  Chung H. Lam

发明人： Louis C. Hsu ,  Brian L. Ji ,  Chung H. Lam

IPC分类号： H03H11/26

CPC分类号： H03H11/24

摘要： A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias conditions for circuits on the IC and in particular, bias on-chip analog circuits. The bias resistance is changed by changing EA resistor phase. Parallel connection of the parallel EA resistors may be dynamically alterable, switching one or more parallel resistors in and out digitally.

摘要翻译： 一个可编程的，电气可变的（EA）电阻器，集成电路（IC）芯片，其中包括EA电阻器和使用片上EA电阻器的集成模拟电路。 相变存储介质在IC上形成电阻器（EA电阻器），其可以形成在并联EA电阻器阵列中，以设置IC上的电路的可变电路偏置条件，特别是片上模拟电路偏置。 通过改变EA电阻相位来改变偏置电阻。 并联EA电阻器的并联连接可以是动态可变的，以数字方式切换一个或多个并联电阻器。

公开(公告)号：US07390730B2

公开(公告)日：2008-06-24

申请号：US11742147

申请日：2007-04-30

申请人： Jack A. Mandelman ,  Louis C. Hsu ,  Rajiv V. Joshi

发明人： Jack A. Mandelman ,  Louis C. Hsu ,  Rajiv V. Joshi

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/10832 ,  H01L27/10858 ,  H01L27/1203 ,  H01L29/94

摘要： A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

摘要翻译： 提供一种具有体电容板的半导体结构，其形成有确保体电容板与源极线（SL）扩散和位线扩散两者自对准的工艺。 因此，SL和位线扩散和体电容板之间的重叠量被精确地控制。 更具体地说，本发明通过使用确保存在1）板和源极/漏极扩散之间的最小重叠的过程形成具有侧壁电容器板的1T无电容的SOI体电荷存储单元的结构，以及2）最小重叠 在本发明中获得的精确控制并且不受对准公差的影响。 与现有技术相比，本发明的电池产生更大的信号余量，改善的性能，更小的芯片尺寸和降低的动态功耗。

公开(公告)号：US07332956B2

公开(公告)日：2008-02-19

申请号：US11163688

申请日：2005-10-27

申请人： Hibourahima Camara ,  Louis C. Hsu ,  James D. Rockrohr ,  Karl D. Selander ,  Huihao Xu ,  Steven J. Zier

发明人： Hibourahima Camara ,  Louis C. Hsu ,  James D. Rockrohr ,  Karl D. Selander ,  Huihao Xu ,  Steven J. Zier

IPC分类号： G05F1/10

CPC分类号： H03K17/223 ,  G05F3/262 ,  G11C5/144 ,  G11C5/145 ,  G11C7/20 ,  H03K17/08

摘要： A system for protecting a weak device operating in micro-electronic circuit that includes a high voltage power supply from high voltage over stressing prevents the weak device from failing during power-up, power-down, and when a low voltage power supply in a multiple power supply system is absent. The system includes a low voltage power supply detection circuit configured to detect circuit power-up, circuit power-down, and when the low voltage power supply is absent, and generate a control signal upon detection. The system further includes a controlled current mirror device configured to provide a trickle current to maintain a conduction channel in the weak device in response to the control signal received from the low voltage power supply detection circuit during circuit power-up, circuit power-down, and when the low voltage power supply is absent.

摘要翻译： 用于保护在微电子电路中操作的弱电装置的系统包括来自高电压过应力的高压电源，防止弱电装置在上电，断电期间发生故障，并且当多个电源中的低电压电源 供电系统不存在。 该系统包括低电压电源检测电路，其被配置为检测电路上电，电路掉电以及当低电压电源不存在时，并且在检测时产生控制信号。 该系统还包括被配置为提供涓流电流的受控电流镜装置，以响应于在电路加电，电路断电期间从低电压电源检测电路接收的控制信号来保持弱装置中的导通通道， 并且当低电压电源不存在时。

公开(公告)号：US07233177B2

公开(公告)日：2007-06-19

申请号：US11098078

申请日：2005-04-04

申请人： Louis C. Hsu ,  Brian L. Ji ,  Chung Hon Lam

发明人： Louis C. Hsu ,  Brian L. Ji ,  Chung Hon Lam

IPC分类号： H03K5/22 ,  G06G7/28

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0064 ,  G11C2013/0054

摘要： The present invention comprises a method and structure for programming an on-chip phase-change resistor to a target resistance. Using an off-chip precision resistor as a reference, a state-machine determines a difference between the resistance of an on-chip resistor and the target resistance. Based upon this difference, the state machine directs a pulse generator to apply set or reset pulses to the on-chip resistor in order to decrease or increase, respectively, the resistance of the resistor, as necessary. In order to program the resistance of the phase-change resistor to a tight tolerance, it is successively reset and set by applying progressively decreasing numbers of reset pulses and set pulses, respectively, until the number of set pulses is equal to one and the target resistance of the on-chip resistor is reached.

摘要翻译： 本发明包括用于将片上相变电阻器编程为目标电阻的方法和结构。 使用片外精密电阻器作为参考，状态机确定片上电阻器的电阻与目标电阻之间的差。 基于这种差异，状态机引导脉冲发生器将片上电阻器设置或复位脉冲施加到片上电阻器，以便根据需要分别降低或增加电阻器的电阻。 为了将相变电阻器的电阻编程为严格的公差，通过分别逐渐递减的复位脉冲数和设定脉冲数来连续复位和设置，直到设定脉冲数等于1，目标值 达到片上电阻的电阻。

公开(公告)号：US08105936B2

公开(公告)日：2012-01-31

申请号：US12173899

申请日：2008-07-16

申请人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

发明人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846

摘要： Solutions for forming dielectric interconnect structures are provided. Specifically, the present invention provides methods of forming a dielectric interconnect structure having a noble metal layer that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma. Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may be provided along an interface between the via and an internal metal layer.

摘要翻译： 提供了用于形成电介质互连结构的解决方案。 具体而言，本发明提供了形成具有直接形成在改性电介质表面上的贵金属层的电介质互连结构的方法。 在典型的实施例中，通过用气态离子等离子体处理互连结构的暴露的电介质层来产生修饰的电介质表面。 在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选胶层上。 此外，贵金属层可以沿通孔和内部金属层之间的界面设置。

公开(公告)号：US08093657B2

公开(公告)日：2012-01-10

申请号：US12181007

申请日：2008-07-28

申请人： Roy Childs Flaker ,  Catherine O'Brien, legal representative ,  Scott Flaker, legal representative ,  Shirley A. Flaker, legal representative ,  Bruce Flaker, legal representative ,  Anne Flaker, legal representative ,  Heather Flaker, legal representative ,  Louis C. Hsu ,  Jente Kuang

发明人： Roy Childs Flaker ,  Louis C. Hsu ,  Jente Kuang

IPC分类号： H01L27/13

CPC分类号： G11C16/08 ,  H01L27/1203

摘要： According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable Vt effect is preserved. The overall body resistance of the individual devices has a minimal effect on the device body potential.

摘要翻译： 根据本发明，公开了一种用于增强SOI制造器件的操作的电路和方法。 在本发明的优选实施例中，提供了一种脉冲放电电路。 这里，电路被设计成提供脉冲，其将在第一访问周期之前将存储器子阵列中的SOI器件的体上的累积电荷放电。 如上所述，一旦累积的电荷已经消散，则消除或大大降低了对存储器子阵列的连续访问的速度损失。 利用适当的控制信号，时序和尺寸，这可以成为解决与SOI负载效应相关的问题的非常有效的方法。 或者，代替将存储器电路中的所有SOI器件的主体连接到地，可以将本地字线驱动器的N沟道FET下拉器件的主体选择性地连接到参考地。 这将使电路能够在克服上述负载问题的同时保留与SOI器件相关联的大部分速度优势。 利用本发明的这个优选实施例，由双极负载效应引起的主要延迟最小化，同时保持由于提供较低的可变Vt效应引起的速度优势。 各个器件的整体体电阻对器件的电位影响最小。

公开(公告)号：US08009461B2

公开(公告)日：2011-08-30

申请号：US11969981

申请日：2008-01-07

申请人： Xu Ouyang ,  Louis C. Hsu

发明人： Xu Ouyang ,  Louis C. Hsu

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A semiconductor device includes a SRAM having a pair of MCSFETs connected as access transistors (pass gates). A design structure embodied or stored in a machine readable medium includes a SRAM having two MCSFETs connected as access transistors.

摘要翻译： 半导体器件包括具有连接作为存取晶体管（通孔）的一对MCSFET的SRAM。 体现或存储在机器可读介质中的设计结构包括具有连接作为存取晶体管的两个MCSFET的SRAM。

公开(公告)号：US07947599B2

公开(公告)日：2011-05-24

申请号：US12018756

申请日：2008-01-23

申请人： Howard H. Chen ,  Louis C. Hsu ,  Lawrence S. Mok ,  J. Campbell Scott

发明人： Howard H. Chen ,  Louis C. Hsu ,  Lawrence S. Mok ,  J. Campbell Scott

IPC分类号： H01L21/44

CPC分类号： H01L21/324 ,  H01L21/268 ,  H01L24/01 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/00

摘要： A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously.

摘要翻译： 公开了一种用于退火具有至少两个堆叠层的层叠半导体结构的激光退火方法。 激光束聚焦在堆叠层的下层。 然后扫描激光束以退火下层中的特征。 然后将激光束聚焦在堆叠层的上层上，并且激光束被扫描以退火上层中的特征。 激光器的波长小于1微米。 激光束的光束尺寸，焦深，能量投射和扫描速度是可编程的。 较低层中的特征偏离上层中的特征，使得这些特征不沿着与激光束的路径平行的平面重叠。 堆叠层中的每一个包括诸如晶体管的有源器件。 此外，第一层和第二层可以同时退火。

公开(公告)号：US07821051B2

公开(公告)日：2010-10-26

申请号：US11625883

申请日：2007-01-23

申请人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis C. Hsu

发明人： Chih-Chao Yang ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis C. Hsu

IPC分类号： H01L27/108

CPC分类号： H01L23/5223 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a MIM capacitor comprising a conformal conductive liner formed on all sidewalls and extending along a bottom of the trench, the bottom of the trench coplanar with the bottom surface of the dielectric layer; an insulating layer formed over a top surface of the conformal conductive liner; and a second plate of the MIM capacitor comprising a core conductor in direct physical contact with the insulating layer, the core conductor filling spaces in the trench not filled by the conformal conductive liner and the insulating layer. The method includes forming portions of the MIM capacitor simultaneously with damascene interconnection wires.

摘要翻译： 一种镶嵌MIM电容器和一种制造MIM电容器的方法。 MIN电容器包括具有顶表面和底表面的电介质层; 电介质层中的沟槽，沟槽从电介质层的顶表面延伸到底表面; MIM电容器的第一板包括形成在所有侧壁上并沿着沟槽的底部延伸的共形导电衬垫，沟槽的底部与电介质层的底表面共面; 绝缘层，形成在所述共形导电衬垫的顶表面上; 以及MIM电容器的第二板，其包括与所述绝缘层直接物理接触的芯导体，所述芯导体填充所述沟槽中的未被所述共形导电衬垫和所述绝缘层填充的空间。 该方法包括与镶嵌互连线同时形成MIM电容器的部分。

公开(公告)号：US07790522B2

公开(公告)日：2010-09-07

申请号：US12543630

申请日：2009-08-19

申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Xu Ouyang

IPC分类号： H01L21/00

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78 ,  H01L29/785 ,  Y10T428/12528

摘要： A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.