公开(公告)号：US10250489B2

公开(公告)日：2019-04-02

申请号：US15635244

申请日：2017-06-28

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Matty Kadosh ,  Gil Levy ,  Aviv Kfir

IPC: H04L12/709 ,  H04L12/753 ,  H04L12/741 ,  H04L12/775 ,  H04L12/721

Abstract: A stacked switch packet communication system is connected to a Multi-Chassis Link Aggregation Group (MLAG). Devices in the system include a designated device for receiving packets that are destined for the MLAG. A new MLAG device is enabled while continuing packet communication by identifying an address of a single port in the new MLAG device. In first updates of the devices the single port is established in the forwarding databases of the devices and the packets transmitted through the devices to the single port. Thereafter, in second updates the single port is replaced in the forwarding databases by another port of the new MLAG device. Upon completion of respective second updates, the packets are transmitted through the devices to the other port in the MLAG.

公开(公告)号：US10230652B2

公开(公告)日：2019-03-12

申请号：US15465626

申请日：2017-03-22

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Zachy Haramaty ,  Barak Gafni ,  Aviv Kfir

IPC: H04L12/26 ,  H04L12/801 ,  H04L12/841

Abstract: A communication system includes a transmit (TX) device and a receive (RX) device. The TX device is configured to transmit data over a communication link. The RX device is configured to receive the data transmitted by the TX device over the communication link, to buffer the received data in an RX buffer, to assess a fill level of the RX buffer, to select, depending on the fill level of the RX buffer, either a pause-resume flow-control scheme or a credit-based flow-control scheme, and to apply the selected flow-control scheme in coordination with the TX device.

公开(公告)号：US10205683B2

公开(公告)日：2019-02-12

申请号：US15081969

申请日：2016-03-28

Applicant: Mellanox Technologies TLV Ltd.

Inventor： George Elias ,  Barak Gafni ,  Ran Ravid ,  Ido Bukspan ,  Zachy Haramaty

IPC: H04L12/24 ,  H04L12/861 ,  H04L12/26 ,  H04L12/825

Abstract: Communication apparatus includes a memory, which is configured to hold data packets, having respective packet sizes, for transmission over a data link, and a transmitter, which is configured to transmit the data packets over the data link at a bit rate determined by a wire speed of the data link. A shaper is coupled to throttle transmission of the data packets by the transmitter responsively to the respective packet sizes, whereby some of the data packets are transmitted over the data link at a transmission rate that is less than the bit rate.

公开(公告)号：US10182017B2

公开(公告)日：2019-01-15

申请号：US15492003

申请日：2017-04-20

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： David Mozes ,  Liron Mula ,  Benny Koren

IPC: H04L12/875 ,  H04L29/06 ,  H04L12/26

Abstract: A network switch includes circuitry, multiple ports and multiple hardware-implemented distinct-flow counters. The multiple ports are configured to receive packets from a communication network. Each of the multiple hardware-implemented distinct-flow counters is configured to receive (i) a respective count definition specifying one or more packet-header fields and (ii) a respective subset of the received packets, and to estimate a respective number of distinct flows that are present in the subset, by evaluating, over the packets in the subset, a number of distinct values in the packet-header fields belonging to the count definition. The circuitry is configured to provide each of the distinct-flow counters with the respective subset of the received packets, including providing a given packet to a plurality of the distinct-flow counters, and to identify an event-of-interest based on numbers of distinct flows estimated by the distinct-flow counters.

公开(公告)号：US10069701B2

公开(公告)日：2018-09-04

申请号：US14994164

申请日：2016-01-13

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： George Elias ,  Barak Gafni ,  Shachar Bar Tikva ,  Roy Kriss ,  Eran Rubinstein

IPC: H04L12/26 ,  H04L12/937 ,  H04L12/933

Abstract: Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A single memory array is coupled to the ports and configured to contain both a respective headroom allocation for each ingress port and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to adjustably allocate to each ingress port a respective volume of memory within the single memory array to serve as the respective headroom allocation, and to queue the data packets in the multiple queues in the single memory array for transmission through the egress ports.

公开(公告)号：US20180241677A1

公开(公告)日：2018-08-23

申请号：US15963118

申请日：2018-04-26

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Eyal Srebro ,  Sagi Kuks ,  Liron Mula ,  Barak Gafni ,  Benny Koren ,  George Elias ,  Itamar Rabenstein ,  Niv Aibester

IPC: H04L12/801 ,  H04L12/863 ,  H04L12/865 ,  H04L12/851 ,  H04L12/927

CPC classification number: H04L47/12 ,  H04L47/2441 ,  H04L47/6215 ,  H04L47/6255 ,  H04L47/6275 ,  H04L47/6295 ,  H04L47/805

Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is less than a selected threshold to a first group, while assigning the flows for which the respective number is equal to or greater than the selected threshold are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.

公开(公告)号：US10009277B2

公开(公告)日：2018-06-26

申请号：US15225859

申请日：2016-08-02

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Dror Goldenberg ,  Alex Shpiner ,  Gil Levy ,  Barak Gafni ,  Shachar Raindel

IPC: H04L12/26 ,  H04L12/801 ,  H04L12/723 ,  H04L12/721 ,  H04L12/835

CPC classification number: H04L47/11 ,  H04L45/50 ,  H04L45/72 ,  H04L47/115 ,  H04L47/30

Abstract: Communication apparatus includes a plurality of interfaces configured to be connected to a Layer-3 packet network and to serve as ingress and egress interfaces to receive and transmit packets from and to the network. Routing logic is coupled to process respective Layer-3 headers of the packets received through the ingress interfaces and to route the packets via the egress interfaces to respective destinations indicated by the Layer-3 headers. Congestion detection logic is coupled to identify a flow of the received packets that is causing congestion in the network and a Layer-3 address from which the flow originates, and to direct the routing logic to route a backward congestion notification message (CNM) packet via one of the egress interfaces to the identified Layer-3 address.

公开(公告)号：US20180091387A1

公开(公告)日：2018-03-29

申请号：US15276823

申请日：2016-09-27

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Lion Levi ,  Gil Levy ,  Zachy Haramaty

IPC: H04L12/26 ,  H04L29/08 ,  H04L12/24

Abstract: A network element includes multiple interfaces and circuitry. The interfaces are configured to connect to a communication system. The circuitry is configured to monitor a respective buffering parameter of data flows received via an ingress interface and queued while awaiting transmission via respective egress interfaces, to identify, based on the respective buffering parameter, at least one data flow for mirroring, to select one or more packets of the identified data flow for analysis by a network manager, and to send the selected packets to the network manager over the communication system via an egress interface.

公开(公告)号：US09876727B2

公开(公告)日：2018-01-23

申请号：US14664944

申请日：2015-03-23

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Chen Gaist ,  Ran Ravid ,  Liron Mulla ,  Avner Hadash

IPC: H04L12/801 ,  H04L12/835 ,  H04L12/841 ,  H04L1/00

CPC classification number: H04L47/35 ,  H04L1/00 ,  H04L1/0002 ,  H04L1/0034 ,  H04L1/18 ,  H04L47/28 ,  H04L47/34

Abstract: A method for communication includes transmitting a sequence of outgoing data blocks from a network node over a communication link to a peer node, and receiving incoming data blocks from the peer node. A control field is added in a predefined location in each of the outgoing data blocks in the sequence by the network node. In at least a first subset of the outgoing data blocks in the sequence, the control field contains error control information, which is capable of causing the peer node to retransmit one or more of the incoming data blocks to the network node, while in at least a second subset of the outgoing data blocks in the sequence, disjoint from the first subset, the control field contains a flow control instruction, configured to cause the peer node to alter a rate of transmission of the incoming data blocks over the link.

公开(公告)号：US20180019947A1

公开(公告)日：2018-01-18

申请号：US15626135

申请日：2017-06-18

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Alexander Shpiner ,  Eitan Zahavi ,  Vladimir Zdornov ,  Tal Anker ,  Matty Kadosh

IPC: H04L12/801 ,  H04L12/707 ,  H04L12/863 ,  H04L12/873

CPC classification number: H04L47/10 ,  H04L45/18 ,  H04L45/22 ,  H04L45/28 ,  H04L47/39 ,  H04L47/524 ,  H04L47/627

Abstract: A credit loop that produces a deadlock is identified in a network of switches that are interconnected for packet traffic flows therethrough. The identification is carried out by periodically transmitting respective credit loop control messages from the loop-participating switches via their deadlock-suspected egress ports to respective next-hop switches. The CLCMs has switch port-unique identifiers (SPUIDs). The loop is identified when in one of the next-hop switches the SPUID of a received CLCM is equal to the SPUID of a transmitted CLCM thereof. A master switch is selected for resolving the deadlock.