Memory array with contact enhancement cap and method for preparing the memory array

    公开(公告)号:US11917813B2

    公开(公告)日:2024-02-27

    申请号:US17528617

    申请日:2021-11-17

    发明人: Ping Hsu

    IPC分类号: H01L27/108 H10B12/00

    摘要: The present disclosure provides a dynamic random access memory (DRAM) array. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.

    SEMICONDUCTOR DEVICE WITH ASSISTANT CAP AND METHOD FOR FABRICATING THE SAME

    公开(公告)号:US20240063285A1

    公开(公告)日:2024-02-22

    申请号:US17892681

    申请日:2022-08-22

    发明人: TSE-YAO HUANG

    IPC分类号: H01L29/45 H01L29/40

    CPC分类号: H01L29/45 H01L29/401

    摘要: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first impurity region positioned in the substrate; a first dielectric layer positioned on the substrate; a first contact including a buried portion positioned along the first dielectric layer and on the first impurity region, and a protruding portion positioned on the buried portion and protruding from the first dielectric layer; a first top assistant cap covering the protruding portion; and a first top conductive layer positioned on the first top assistant cap. The first top assistant cap includes germanium or silicon germanium.

    Method for manufacturing semiconductor device with bit line contacts of different pitches

    公开(公告)号:US11903186B2

    公开(公告)日:2024-02-13

    申请号:US17726004

    申请日:2022-04-21

    IPC分类号: H10B12/00

    摘要: A semiconductor device and method for manufacturing the same are provided. The method includes providing a substrate including a plurality of active areas separated from each other. In some embodiments, the method also includes forming first mask structures on the substrate. In some embodiments, the method further includes forming a first protective layer covering the first mask structures and the substrate. In some embodiments, the first protective layer defines an area exposing a portion of the first mask structures and the substrate, and the area defined by the first protective layer has a zigzag edge in a top view. In addition, the method includes performing a first etching process to remove a portion of the substrate exposed from the first mask structures and the first protective layer to form trenches.