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71.
公开(公告)号:US20240071842A1
公开(公告)日:2024-02-29
申请号:US17898116
申请日:2022-08-29
发明人: Tsai-Wei LIN
IPC分类号: H01L21/66 , G03F7/20 , G03F9/00 , H01L21/768 , H01L23/544
CPC分类号: H01L22/30 , G03F7/70 , G03F9/7046 , H01L21/76885 , H01L22/12 , H01L23/544 , H01L21/32139 , H01L2223/54426
摘要: The present disclosure provides a semiconductor structure, a method of manufacturing the semiconductor structure and a system for manufacturing the semiconductor structure. The method includes several operations. A substrate including a device region and a scribe line region is provided. A first layer is formed over the substrate. A first photoluminescent layer is formed over the first layer in the scribe line region. The first layer and the first photoluminescent layer are patterned to form a first pattern in the scribe line region. A first patterned mask layer is formed over a second layer. An alignment of the first patterned mask layer with the first pattern is detected. A pattern of the first patterned mask layer is transferred to the second layer to form a second pattern in the scribe line region.
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公开(公告)号:US11917813B2
公开(公告)日:2024-02-27
申请号:US17528617
申请日:2021-11-17
发明人: Ping Hsu
IPC分类号: H01L27/108 , H10B12/00
CPC分类号: H10B12/315 , H10B12/0335 , H10B12/053 , H10B12/34
摘要: The present disclosure provides a dynamic random access memory (DRAM) array. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.
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73.
公开(公告)号:US20240064961A1
公开(公告)日:2024-02-22
申请号:US17821464
申请日:2022-08-22
发明人: YU XIAO
IPC分类号: H10B12/00
CPC分类号: H10B12/312 , H10B12/482 , H10B12/488 , H10B12/03
摘要: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a word line, a channel layer, and a bit line. The word line is disposed on the substrate. The channel layer is surrounded by the word line. The bit line is disposed on the channel layer. The channel layer has a first portion in the substrate and a second portion over the substrate. A first width of the first portion is greater than a second width of the second portion along a first direction.
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公开(公告)号:US20240063285A1
公开(公告)日:2024-02-22
申请号:US17892681
申请日:2022-08-22
发明人: TSE-YAO HUANG
CPC分类号: H01L29/45 , H01L29/401
摘要: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first impurity region positioned in the substrate; a first dielectric layer positioned on the substrate; a first contact including a buried portion positioned along the first dielectric layer and on the first impurity region, and a protruding portion positioned on the buried portion and protruding from the first dielectric layer; a first top assistant cap covering the protruding portion; and a first top conductive layer positioned on the first top assistant cap. The first top assistant cap includes germanium or silicon germanium.
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75.
公开(公告)号:US20240063115A1
公开(公告)日:2024-02-22
申请号:US17891421
申请日:2022-08-19
发明人: WEI-ZHONG LI , HSIH-YANG CHIU
IPC分类号: H01L23/525 , H01L23/528 , H01L29/08 , H01L29/417 , H01L29/423 , H01L27/088 , H01L21/8234
CPC分类号: H01L23/5256 , H01L23/5283 , H01L29/0847 , H01L29/41775 , H01L29/42356 , H01L27/088 , H01L21/823425 , H01L21/823475 , H01L21/823481
摘要: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a transistor disposed over the substrate; and a trench fuse disposed in the substrate and penetrating a source/drain (S/D) region of the transistor. A method for manufacturing the semiconductor structure is also provided.
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76.
公开(公告)号:US11903186B2
公开(公告)日:2024-02-13
申请号:US17726004
申请日:2022-04-21
发明人: Yu-Ting Lin , Huei-Ru Lin
IPC分类号: H10B12/00
CPC分类号: H10B12/485 , H10B12/033 , H10B12/053 , H10B12/315 , H10B12/34 , H10B12/482
摘要: A semiconductor device and method for manufacturing the same are provided. The method includes providing a substrate including a plurality of active areas separated from each other. In some embodiments, the method also includes forming first mask structures on the substrate. In some embodiments, the method further includes forming a first protective layer covering the first mask structures and the substrate. In some embodiments, the first protective layer defines an area exposing a portion of the first mask structures and the substrate, and the area defined by the first protective layer has a zigzag edge in a top view. In addition, the method includes performing a first etching process to remove a portion of the substrate exposed from the first mask structures and the first protective layer to form trenches.
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公开(公告)号:US11903180B2
公开(公告)日:2024-02-13
申请号:US17700406
申请日:2022-03-21
发明人: Cheng-Yan Ji , Wei-Tong Chen
IPC分类号: H10B12/00
CPC分类号: H10B12/053 , H10B12/34
摘要: A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate having a trench. The method also includes forming a first buffer layer in the trench. The method further includes forming a doped-polysilicon layer on the first buffer layer in the trench. The method also includes performing a thermal treatment on the doped-polysilicon layer.
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公开(公告)号:US20240047395A1
公开(公告)日:2024-02-08
申请号:US17818003
申请日:2022-08-08
发明人: Sheng-Fu HUANG , Shing-Yih SHIH
IPC分类号: H01L23/00 , H01L25/065
CPC分类号: H01L24/08 , H01L25/0657 , H01L24/05 , H01L2225/06524 , H01L2225/06541 , H01L2924/3511 , H01L2224/08145 , H01L2224/05687 , H01L2224/0236 , H01L2224/0235 , H01L2224/08146 , H01L2224/02371 , H01L2224/02373 , H01L2224/02381 , H01L2224/024
摘要: A semiconductor structure includes a first chip and a second chip bonded to the first chip. The first chip includes a first semiconductor substrate, a first multi-level interconnect structure over the first semiconductor substrate, a first redistribution layer (RDL) over a conductive line of the first multi-level interconnect structure, a compact layer over the first RDL and the first multi-level interconnect structure, a cap layer over the compact layer, and a metal pad on the first RDL. The second chip includes a second semiconductor substrate, a second multi-level interconnect structure over the second semiconductor substrate, and conductive structure extending from the second multi-level interconnect structure to the metal pad.
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79.
公开(公告)号:US20240047358A1
公开(公告)日:2024-02-08
申请号:US17881843
申请日:2022-08-05
发明人: TSE-YAO HUANG
IPC分类号: H01L23/532 , H01L23/528 , H01L21/311 , H01L21/3115 , H01L21/3205
CPC分类号: H01L23/53271 , H01L23/5283 , H01L23/5329 , H01L21/31111 , H01L21/31155 , H01L21/32055
摘要: A semiconductor device structure includes a first lower semiconductor structure disposed over a semiconductor substrate. The first lower semiconductor structure has a first sidewall and a second sidewall opposite to the first sidewall. The semiconductor device structure also includes a first upper semiconductor structure covering a top surface and the first sidewall of the first lower semiconductor structure. The first lower semiconductor structure and the first upper semiconductor structure include different materials. The semiconductor device structure further includes a first oxide portion disposed over the semiconductor substrate and extending along the second sidewall of the first lower semiconductor structure. The first oxide portion has an L-shape.
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80.
公开(公告)号:US20240047354A1
公开(公告)日:2024-02-08
申请号:US17879995
申请日:2022-08-03
发明人: MIN-CHUNG CHENG
IPC分类号: H01L23/528 , H01L23/522 , H01L21/768
CPC分类号: H01L23/5283 , H01L23/5226 , H01L21/76816 , H01L21/76831 , H01L21/76843 , H01L21/76877
摘要: The present application provides a wiring structure, a semiconductor device having the wiring structure, and a method of manufacturing the semiconductor device. The wiring structure includes a substrate, a metallic layer above the substrate, at least one first conductive feature and at least one second conductive feature. The first and second conductive features are disposed between the substrate and the metallic layer; the first conductive feature has a first critical dimension, and the second conductive feature has a second critical dimension less than the first critical dimension. An effective resistance of the wiring structure can be adjusted by changing the critical dimensions of the first and second conductive features. The semiconductor device including the wiring structure and a method of manufacturing the semiconductor device are also provided.
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