公开(公告)号：US11348914B2

公开(公告)日：2022-05-31

申请号：US16277161

申请日：2019-02-15

Applicant: SOCIONEXT INC.

Inventor： Teruo Suzuki

IPC: H01L27/02

Abstract: A semiconductor device includes: a first domain including a first high power source line, a first low power source line, and a first power clamp circuit; a second domain including a second high power source line, a second low power source line, and a second power clamp circuit; a third power clamp circuit provided between the second high power source line and the first low power source line; a first relay circuit that receives a signal from the first domain and outputs the signal to the second domain; and a second relay circuit that receives a signal from the second domain and outputs the signal to the first domain, wherein the first relay circuit and the second relay circuit have a circuit portion that is connected to the second high power source line and the first low power source line.

公开(公告)号：US11335814B2

公开(公告)日：2022-05-17

申请号：US17095593

申请日：2020-11-11

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L27/00 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/118 ,  H01L29/06 ,  H01L29/775 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/12

Abstract: Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

公开(公告)号：US20220148991A1

公开(公告)日：2022-05-12

申请号：US17580371

申请日：2022-01-20

Applicant: SOCIONEXT INC.

Inventor： Takumi IHARA ,  Masanori NATSUAKI

IPC: H01L23/00 ,  H01L23/498

Abstract: A semiconductor device includes a wiring board, a semiconductor chip arranged on the wiring board, and a plurality of bumps arranged between the wiring board and the semiconductor chip, wherein the wiring board includes a first conductor, a second conductor, a third conductor, a first via, a second via, and a third via, wherein the second conductor is arranged at a position closer to a center of the semiconductor chip than the first conductor is to the center, as seen in a thickness direction, the first conductor and the second conductor are arranged next to each other without another conductor interposed therebetween, as seen in the thickness direction, and a first distance between the first conductor and the second conductor is larger than a second distance between the first conductor and the third conductor.

公开(公告)号：US11329019B2

公开(公告)日：2022-05-10

申请号：US16950789

申请日：2020-11-17

Applicant: SOCIONEXT INC.

Inventor： Takumi Ihara ,  Masanori Natsuaki

IPC: H01L23/00 ,  H01L23/498

Abstract: A semiconductor device includes a wiring board, a semiconductor chip arranged on the wiring board, and a plurality of bumps arranged between the wiring board and the semiconductor chip, wherein the wiring board includes a first conductor, a second conductor, a third conductor, a first via, a second via, and a third via, wherein the second conductor is arranged at a position closer to a center of the semiconductor chip than the first conductor is to the center, as seen in a thickness direction, the first conductor and the second conductor are arranged next to each other without another conductor interposed therebetween, as seen in the thickness direction, and a first distance between the first conductor and the second conductor is larger than a second distance between the first conductor and the third conductor.

公开(公告)号：US20220117578A1

公开(公告)日：2022-04-21

申请号：US17567507

申请日：2022-01-03

Applicant: Socionext Inc.

Inventor： Naoto ADACHI ,  Hiroshi KISHI ,  Hiroaki TAKAGI

IPC: A61B8/00

Abstract: An ultrasonic probe includes a wireless transmitter-receiver configured to perform communication through a wireless network having a plurality of channels and obtain identification information of apparatuses connected to the wireless network from the apparatuses; a memory configured to store identification information for identifying other ultrasonic probes from among the apparatuses; and a processor configured to count other ultrasonic probes connected with the wireless network on a per channel basis with respect to the plurality of channels based on the identification information obtained by the wireless transmitter-receiver and the identification information stored in the memory, and determine to connect to a channel at which the number of the other ultrasonic probes counted by the processor is smallest.

公开(公告)号：US11308916B2

公开(公告)日：2022-04-19

申请号：US17124111

申请日：2020-12-16

Applicant: SOCIONEXT INC.

Inventor： Katsuya Otoi

IPC: G09G5/10 ,  G09G3/3208

Abstract: A luminance determining method of determining a luminance of each pixel in a display device that includes a self emitting element includes dividing one image into a plurality of blocks that do no overlap each other; and correcting, in each of the plurality of blocks, a luminance of each pixel by reducing the luminance in the plurality of blocks through a correction method determined for each of the plurality of blocks.

公开(公告)号：US11289610B2

公开(公告)日：2022-03-29

申请号：US17125532

申请日：2020-12-17

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki Shimbo

IPC: H01L21/70 ,  H01L29/786 ,  H01L27/092 ,  B82Y10/00 ,  H01L27/02 ,  H01L29/06 ,  H01L27/118 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/775

Abstract: In a standard cell including nanowire FETs, pads connected to nanowires are arranged at a predetermined pitch in X direction along which the nanowires extend. A cell width of the standard cell is an integral multiplication of the pitch. In a case where the standard cell is arranged to constitute the layout of a semiconductor integrated circuit device, the pads are regularly arranged in the X direction.

公开(公告)号：US20220094345A1

公开(公告)日：2022-03-24

申请号：US17457457

申请日：2021-12-03

Applicant: Socionext Inc.

Inventor： Masanori OKINOI

IPC: H03K5/135 ,  H03K5/14

Abstract: A variable delay circuit includes at least one first delay circuit and a second delay circuit. The first delay circuit includes multiple first delay elements connected in series and is configured to output a delay signal from a first stage first delay element that is a first stage of the first delay circuit. The second delay circuit includes at least one second delay element and multiple third delay elements connected in series. The second delay circuit is configured to output a delay signal from a first stage second delay element that is a first stage of the second delay circuit. The first stage first delay element and the first stage second delay element are connected in series. A delay signal obtained by delaying an input signal received at one circuit among the first delay circuit and the second delay circuit for a predetermined time duration is output from another circuit.

公开(公告)号：US20220093613A1

公开(公告)日：2022-03-24

申请号：US17539695

申请日：2021-12-01

Applicant: Socionext Inc.

Inventor： Shinichi MORIWAKI

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775

Abstract: Transistors N1, N5 corresponding to a drive transistor PD1 are formed in a cell lower part and a cell upper part, respectively, and transistors N2, N6 corresponding to a drive transistor PD2 are formed in the cell lower part and the cell upper part, respectively. A transistor P1 corresponding to a load transistor PU2 is formed in the cell lower part, and a transistor P2 corresponding to a load transistor PU1 is formed in the cell upper part.

公开(公告)号：US20220077137A1

公开(公告)日：2022-03-10

申请号：US17467069

申请日：2021-09-03

Applicant: SOCIONEXT INC.

Inventor： Hidetoshi TANAKA ,  Mai Tsukamoto

IPC: H01L27/02 ,  H01L23/522

Abstract: A semiconductor device includes a pad portion, a protection circuit, N wiring layers, and conductive vias connecting adjacent wiring layers, wherein, in a plan view, the semiconductor device includes a first area, a second area, and a third area, wherein the N wiring layers are provided to extend over the first area, the second area, and the third area, wherein a first wiring layer on a side of the pad portion is connected to the pad portion in the first area, and wherein an N-th wiring layer on a side of the protection circuit is connected to the protection circuit in the second area, and in the second area and the third area, where a total cross-sectional area of i-th conductive vias connecting an i-th wiring layer and an (i+1)-th wiring layer is denoted as Si, S1 is smaller than Sj for any j (j being 2 or more).