公开(公告)号：US07656380B2

公开(公告)日：2010-02-02

申请号：US09970929

申请日：2001-10-05

申请人： Jun Koyama ,  Tomoaki Atsumi ,  Hiroyuki Miyake

发明人： Jun Koyama ,  Tomoaki Atsumi ,  Hiroyuki Miyake

IPC分类号： G09G3/36 ,  G11C19/00

CPC分类号： G09G3/3688 ,  G09G3/3677 ,  G09G5/02 ,  G09G2310/0283 ,  G09G2310/0289 ,  G09G2330/021 ,  H01L27/12 ,  H01L27/1214

摘要： This invention provides a driving circuit for a display device, for accomplishing low power consumption by use of a level shifter capable of reliably converting signals having low voltage amplitude. A source signal line driving circuit is divided into a plurality of units. Pulses outputted from a shift register, etc, are used to execute ON/OFF control of the operation of a current supply source to the level shifter of each divided unit. The supply of the current to the level shifter is suspended in the stage not containing the circuit that outputs the pulses, but is made to only the unit including the shift register of the operating stage. In consequence, low power consumption can be achieved.

摘要翻译： 本发明提供一种用于显示装置的驱动电路，用于通过使用能够可靠地转换具有低电压幅度的信号的电平转换器来实现低功耗。 源极信号线驱动电路被分成多个单元。 从移位寄存器等输出的脉冲用于对每个分割单元的电平移位器执行电流源的操作的ON / OFF控制。 向电平移位器的电流的供给被暂停在不包含输出脉冲的电路的级中，但是仅被构成包括操作级的移位寄存器的单元。 因此，可以实现低功耗。

公开(公告)号：US07430146B2

公开(公告)日：2008-09-30

申请号：US11554128

申请日：2006-10-30

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/22

摘要： The semiconductor device in which reading and writing of data can be accurately performed by preventing malfunction even when a selection of address delays. The semiconductor device has three factors of a data holding unit, a precharge unit and a delay unit. The data holding unit includes a plurality of memory cells. The precharge unit includes a precharge potential line, a precharge signal line and a plurality of switches. The delay unit includes a plurality of transistors. In addition, it has one or both of an address selecting unit having a column-decoder and a row-decoder and a display unit having a plurality of pixels, as well as the three factors.

摘要翻译： 即使在选择地址延迟的情况下，也可以通过防止故障来准确地执行数据的读取和写入的半导体装置。 半导体器件具有数据保持单元，预充电单元和延迟单元的三个因素。 数据保持单元包括多个存储单元。 预充电单元包括预充电电位线，预充电信号线和多个开关。 延迟单元包括多个晶体管。 此外，它具有地址选择单元，其具有列解码器和行解码器以及具有多个像素的显示单元以及三个因素中的一个或两个。

公开(公告)号：US20080088367A1

公开(公告)日：2008-04-17

申请号：US11576585

申请日：2005-10-05

申请人： Tomoaki Atsumi

发明人： Tomoaki Atsumi

IPC分类号： H03D3/00

CPC分类号： H04L7/0331 ,  G06K19/0723

摘要： The invention provides a semiconductor device that generates a clock signal with a fixed pulse width from a carrier. The invention also provides a semiconductor device where data can be obtained accurately from a carrier using a clock signal with a fixed pulse width. Further, the invention provides a semiconductor device that has a simpler circuit configuration and a smaller scale, and consumes less power as compared to the PLL circuit. According to the invention, a signal obtained by dividing a carrier including 100% modulation is not used as a clock signal, and a correction circuit is used to generate a clock signal using a demodulated signal and a signal obtained by dividing the carrier including 100% modulation. According to the invention having such a configuration, a clock signal with a fixed pulse width can be generated.

摘要翻译： 本发明提供一种从载体产生具有固定脉冲宽度的时钟信号的半导体器件。 本发明还提供一种半导体器件，其中可以使用具有固定脉冲宽度的时钟信号从载波精确地获得数据。 此外，本发明提供一种与PLL电路相比具有更简单的电路配置和更小规模的半导体器件，并且消耗更少的功率。 根据本发明，通过对包含100％调制的载波进行分频而获得的信号不被用作时钟信号，并且使用校正电路来产生使用解调信号的时钟信号和通过将包含100％ 调制。 根据具有这种结构的本发明，可以产生具有固定脉冲宽度的时钟信号。

公开(公告)号：US20070229228A1

公开(公告)日：2007-10-04

申请号：US11716042

申请日：2007-03-09

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Masato Ishii ,  Tomoaki Atsumi ,  Takeshi Osada ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Yutaka Shionoiri

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Masato Ishii ,  Tomoaki Atsumi ,  Takeshi Osada ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa ,  Yutaka Shionoiri

IPC分类号： H04Q5/22

CPC分类号： G06K19/0723 ,  G06K19/0701 ,  G06K19/0702

摘要： To provide a semiconductor device including an RFID which can transmit and receive individual information without checking of the remaining charge of a battery or a replacing operation of the battery in accordance with deterioration over time of the battery for driving, and can maintain an excellent state for transmission and reception of individual information even when power of a radio wave or an electromagnetic wave from outside is insufficient. A battery (also described as a secondary battery) is provided as a power supply for supplying power to the RFID. Then, when power which is obtained from a signal received from outside is larger than predetermined power, its surplus power is stored in the battery; and when the power which is obtained from the signal received from outside is smaller than the predetermined power, power which is obtained from the battery is used for the power for driving.

摘要翻译： 为了提供一种包括RFID的半导体器件，其可以根据用于驱动的​​电池的劣化随时检测电池的剩余电量或电池的替换操作而发送和接收各个信息，并且可以保持优异的状态 即使在来自外部的无线电波或电磁波的功率不足的情况下，也可以发送和接收个别信息。 提供电池（也称为二次电池）作为向RFID提供电力的电源。 然后，当从外部接收的信号获得的功率大于预定功率时，其剩余功率被存储在电池中; 并且当从外部接收的信号获得的功率小于预定功率时，从电池获得的功率用于驱动电力。

公开(公告)号：US20070126059A1

公开(公告)日：2007-06-07

申请号：US11607022

申请日：2006-12-01

申请人： Hiroki Dembo ,  Tomoaki Atsumi

发明人： Hiroki Dembo ,  Tomoaki Atsumi

IPC分类号： H01L29/76

CPC分类号： G06K7/0008 ,  G06K7/10029 ,  G06K19/0723 ,  H01L27/092 ,  H01L27/1214 ,  H01L27/1266 ,  H01L27/13

摘要： An object is to provide a semiconductor device which includes an anti-collision function during or after production of an IC chip just by a change of a program, even when there is a change of a specification of a product accompanying a change of the kind or standard of a signal of a wireless means for each product. A semiconductor device includes an arithmetic circuit and a circuit for transmitting/receiving a signal to/from outside. The arithmetic circuit includes a central processing unit, a random access memory, a read only memory, and a controller. The read only memory stores a program for processing collision avoidance in transmitting/receiving the signal to/from outside. The program is executed in the central processing unit, so that the arithmetic circuit processes collision avoidance.

摘要翻译： 本发明的目的是提供一种半导体器件，其仅在通过程序改变而在IC芯片制造期间或之后包括防冲突功能，即使当伴随着该类型的改变的产品的规格的变化 每个产品的无线装置的信号标准。 半导体器件包括运算电路和用于向/从外部发送/接收信号的电路。 算术电路包括中央处理单元，随机存取存储器，只读存储器和控制器。 只读存储器存储用于在向/从外部发送/接收信号时处理防冲突的程序。 该程序在中央处理单元中执行，使得运算电路处理避免冲突。

公开(公告)号：US20070109247A1

公开(公告)日：2007-05-17

申请号：US11622510

申请日：2007-01-12

申请人： Jun KOYAMA ,  Tomoaki Atsumi ,  Hiroyuki Miyake

发明人： Jun KOYAMA ,  Tomoaki Atsumi ,  Hiroyuki Miyake

IPC分类号： G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0809 ,  G09G2300/0828 ,  G09G2300/0842 ,  G09G2300/0857

摘要： A liquid crystal display device with low power consumption is provided. In the liquid crystal display device having a source signal line driver circuit, a gate signal line driver circuit, a DAC controller, and a pixel portion and performing an image display using an n-bit (n is a natural number, n≧2) digital image signal, one pixel has memory circuits for storing an n-bit digital image signal and a D/A converter, and the n-bit digital image signal for one frame can be stored in the pixel. In case of a static image display, the image signal stored in the memory circuits is read out every frame to perform the display, and thus, only a DAC controller is driven during the display. Therefore, this contributes to a reduction of the power consumption of the entire liquid crystal display device.

摘要翻译： 提供具有低功耗的液晶显示装置。 在具有源极信号线驱动电路，栅极信号线驱动电路，DAC控制器和像素部分的液晶显示装置中，使用n位（n为自然数，n> = 2）进行图像显示 ）数字图像信号，一个像素具有用于存储n位数字图像信号和D / A转换器的存储电路，并且用于一帧的n位数字图像信号可以存储在像素中。 在静态图像显示的情况下，每帧读出存储在存储器电路中的图像信号以进行显示，因此在显示期间仅驱动DAC控制器。 因此，这有助于降低整个液晶显示装置的功耗。

公开(公告)号：US20070089028A1

公开(公告)日：2007-04-19

申请号：US11533169

申请日：2006-09-19

申请人： Masafumi ITO ,  Tomoaki ATSUMI

发明人： Masafumi ITO ,  Tomoaki ATSUMI

IPC分类号： H03M13/00

CPC分类号： H03M13/09 ,  H04B1/10

摘要： An object of the present invention is to provide a CRC circuit with more simple structure and low power consumption. The CRC circuit includes a first shift register to a p-th shift register, a first EXOR to a (p−1)th EXOR, and a switching circuit. A data signal, a select signal, and an output of a last stage of the p-th shift register are inputted to the switching circuit, and the switching circuit switches a first signal or a second signal in response to the select signal to be outputted.

摘要翻译： 本发明的目的是提供一种具有更简单的结构和低功耗的CRC电路。 CRC电路包括到第p移位寄存器的第一移位寄存器，第一EXOR到第（p-1）个EXOR和开关电路。 数据信号，选择信号和第p移位寄存器的最后级的输出被输入到开关电路，并且开关电路响应于要输出的选择信号而切换第一信号或第二信号 。

公开(公告)号：US20070076515A1

公开(公告)日：2007-04-05

申请号：US11607053

申请日：2006-12-01

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C8/00

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。

公开(公告)号：US20060121652A1

公开(公告)日：2006-06-08

申请号：US11276105

申请日：2006-02-14

申请人： Satoshi Murakami ,  Yosuke Tsukamoto ,  Tomoaki Atsumi ,  Masayuki Sakakura

发明人： Satoshi Murakami ,  Yosuke Tsukamoto ,  Tomoaki Atsumi ,  Masayuki Sakakura

IPC分类号： H01L21/84

CPC分类号： H01L29/04 ,  G02F1/13454 ,  G02F1/136204 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124

摘要： In manufacturing a semiconductor device, static electricity is generated while contact holes are formed in an interlayer insulating film by dry etching. Damage to a pixel region or a driving circuit region due to travel of the static electricity generated is prevented. Gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage.

摘要翻译： 在制造半导体器件时，通过干蚀刻在层间绝缘膜中形成接触孔时产生静电。 防止了由于所产生的静电的行进而对像素区域或驱动电路区域的损害。 栅极信号线在结晶半导体膜之上彼此间隔开。 因此，当在层间绝缘膜中打开接触孔时，第一保护电路不电连接。 在干蚀刻期间产生的用于打开接触孔的静电从栅极信号线移动，损坏栅极绝缘膜，通过晶体半导体膜，并且在栅极绝缘膜到达栅极信号线之前再次损坏栅极绝缘膜。 由于在干蚀刻期间产生的静电损害第一保护电路，所以静电的能量减小，直到损失驱动电路TFT的能力。 从而防止了驱动电路TFT遭受静电放电损坏。

公开(公告)号：US20050047266A1

公开(公告)日：2005-03-03

申请号：US10890173

申请日：2004-07-14

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C17/18 ,  G11C7/10 ,  G11C7/12 ,  G11C8/00 ,  G11C11/4094 ,  G11C11/418 ,  G11C11/419 ,  G11C17/08 ,  G11C17/12 ,  H03K17/00 ,  H03K17/687 ,  H03K17/693

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。