公开(公告)号：US6074923A

公开(公告)日：2000-06-13

申请号：US107583

申请日：1998-06-09

申请人： Tzung-Han Lee

发明人： Tzung-Han Lee

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76838 ,  H01L29/66545 ,  H01L29/6659

摘要： A method of manufacturing a MOS transistor begins with the provision of a semiconductor substrate. A gate oxide layer, a polysilicon layer and a silicon nitride layer are sequentially formed over the substrate. Next, the gate oxide layer, the polysilicon layer and the silicon nitride layer are patterned to form a gate structure. Subsequently, spacers are formed covering the sidewalls of the gate oxide layer, the polysilicon layer and the silicon nitride layer. Thereafter, a dielectric layer is formed, and covers the semiconductor substrate, the silicon nitride layer and the spacers. Next, a planarization operation is carried out to remove a portion of the dielectric layer. Planarization continues until the silicon nitride layer is exposed. After that, the silicon nitride layer is removed, exposing the polysilicon layer, and then a glue layer is formed over the dielectric layer and the polysilicon layer. Finally, a conductive layer is formed over the glue layer to complete the fabrication of the MOS transistor.

摘要翻译： 制造MOS晶体管的方法开始于提供半导体衬底。 在衬底上顺序地形成栅氧化层，多晶硅层和氮化硅层。 接下来，栅极氧化物层，多晶硅层和氮化硅层被图案化以形成栅极结构。 随后，形成覆盖栅极氧化物层，多晶硅层和氮化硅层的侧壁的间隔物。 此后，形成电介质层，并覆盖半导体衬底，氮化硅层和间隔物。 接下来，进行平面化操作以去除电介质层的一部分。 平面化继续直到氮化硅层露出。 之后，去除氮化硅层，暴露多晶硅层，然后在电介质层和多晶硅层上形成胶层。 最后，在胶层上形成导电层以完成MOS晶体管的制造。

公开(公告)号：US6017662A

公开(公告)日：2000-01-25

申请号：US181298

申请日：1998-10-28

申请人： Tzung-Han Lee

发明人： Tzung-Han Lee

IPC分类号： H01L23/544 ,  H01L23/58 ,  G03F9/00

CPC分类号： H01L23/585 ,  H01L23/544 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A method of reducing laser mark peeling depends on what sort of layer lies over the laser mark. If a structure formed on the laser mark is a conductive layer, an adhesion layer or a passivation layer, the conductive layer, adhesion layer or passivation layer is removed from the laser mark. If a structure formed on a laser mark is a dielectric layer, the dielectric layer is left on the laser mark. The area removed from the upper layer is equal to or bigger than the area removed from the lower layer in order to avoid contacts between the conductive layers. In addition to being used for a laser mark, the method mentioned above can be also used for a wafer edge and an alignment mark.

摘要翻译： 减少激光标记剥离的方法取决于激光标记上的层是什么。 如果在激光标记上形成的结构是导电层，粘合层或钝化层，则从激光标记去除导电层，粘合层或钝化层。 如果在激光标记上形成的结构是电介质层，则介电层留在激光标记上。 从上层除去的面积等于或大于从下层去除的面积，以避免导电层之间的接触。 除了用于激光标记之外，上述方法也可以用于晶片边缘和对准标记。

公开(公告)号：US5994201A

公开(公告)日：1999-11-30

申请号：US170436

申请日：1998-10-13

申请人： Tzung-Han Lee

发明人： Tzung-Han Lee

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/76229 ,  Y10S148/05

摘要： A method for manufacturing shallow trench isolation regions according to the invention uses a first stop layer and a second stop layer as two polishing stop layers, or a polishing stop layer and an etching stop layer, respectively. By performing chemical mechanical polishing twice, or performing chemical mechanical polishing one time and then etch back, the influence on subsequently formed shallow trench isolation regions caused by different sizes and densities thereof can be greatly alleviated.

摘要翻译： 根据本发明的用于制造浅沟槽隔离区的方法使用第一阻挡层和第二阻挡层作为两个抛光停止层，或抛光停止层和蚀刻停止层。 通过进行两次化学机械抛光或进行一次化学机械抛光，然后进行回蚀，可以大大减轻由不同尺寸和密度引起的随后形成的浅沟槽隔离区的影响。

公开(公告)号：US5962342A

公开(公告)日：1999-10-05

申请号：US993870

申请日：1997-12-18

申请人： Andy Chuang ,  Tzung-Han Lee

发明人： Andy Chuang ,  Tzung-Han Lee

IPC分类号： H01L21/762 ,  H01L21/00

CPC分类号： H01L21/76232

摘要： An adjustable method for making trenches for a semiconductor IC device having eliminated top corners is disclosed. The adjustable method includes forming a masking layer on the surface of the silicon nitride layer covering the device substrate that has openings corresponding to the openings of the trenches formed. Dimension of the masking layer opening is relatively greater than the dimension of the opening of the corresponding trench. An anisotropic etching procedure is then performed against the portions of the device substrate exposed out of the coverage of the masking layer, and the anisotropic etching shapes the trench sidewalls into sloped ones having larger dimension at the opening than at the surface of the filling material inside the trenches. This eliminates the top corners at the edges of the trench opening, charge accumulation and consequent leakage current can thus be prevented.

摘要翻译： 公开了一种用于制造消除顶角的半导体IC器件的沟槽的可调节方法。 可调方法包括在覆盖器件基板的表面上形成掩模层，该掩模层具有与形成的沟槽的开口对应的开口。 掩模层开口的尺寸相对大于相应沟槽开口的尺寸。 然后针对暴露在掩模层的覆盖范围内的器件衬底的部分执行各向异性蚀刻过程，并且各向异性蚀刻将沟槽侧壁形成在开口处具有比在填充材料内部的表面处具有更大尺寸的倾斜的侧壁 壕沟 这消除了沟槽开口边缘的顶角，从而可以防止电荷累积和随之而来的泄漏电流。

公开(公告)号：US20130146954A1

公开(公告)日：2013-06-13

申请号：US13429448

申请日：2012-03-26

申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L27/0207 ,  H01L27/10876 ,  H01L27/10885

摘要： The present invention provides a memory array including a substrate, an isolation region, a plurality of active regions, a plurality of buried bit lines, a plurality of word lines, a plurality of drain regions and a plurality of capacitors. The isolation region and the active regions are disposed in the substrate and the active regions are encompassed and isolated by the isolation region. The buried bit lines are disposed in the substrate and extend in the second direction. The word lines are disposed in the substrate extend in the first direction. The drain regions are disposed in the active region not covered by the word lines. The capacitors are disposed on the substrate and electrically connected to the drain regions.

摘要翻译： 本发明提供了一种存储器阵列，其包括衬底，隔离区，多个有源区，多个掩埋位线，多个字线，多个漏极区和多个电容。 隔离区域和有源区域设置在衬底中，并且有源区域被隔离区域包围和隔离。 掩埋位线设置在基板中并沿第二方向延伸。 字线设置在基板中沿第一方向延伸。 漏极区域设置在未被字线覆盖的有源区域中。 电容器设置在基板上并电连接到漏极区域。

公开(公告)号：US20130059442A1

公开(公告)日：2013-03-07

申请号：US13282593

申请日：2011-10-27

申请人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG

发明人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG

IPC分类号： H01L21/302

CPC分类号： H01L21/3065 ,  H01L21/3081 ,  H01L21/3083

摘要： A method for adjusting the trench depth of a substrate has the steps as follows. Forming a patterned covering layer on the substrate, wherein the patterned covering layer defines a wider spacing and a narrower spacing. Forming a wider buffering layer arranged in the wider spacing and a narrower buffering layer arranged in the narrower spacing. The thickness of the narrower buffering layer is thinner than the wider buffering layer. Implementing dry etching process to make the substrate corresponding to the wider and the narrower buffering layers form a plurality of trenches. When etching the wider and the narrower buffering layers, the narrower buffering layer is removed firstly, so that the substrate corresponding to the narrower buffering layer will be etched early than the substrate corresponding to the wider buffering layer.

摘要翻译： 用于调整衬底的沟槽深度的方法具有以下步骤。 在衬底上形成图案化的覆盖层，其中图案化覆盖层限定更宽的间隔和更窄的间隔。 形成更宽的间隔布置的较宽的缓冲层和以较窄的间隔布置的较窄的缓冲层。 较窄的缓冲层的厚度比较宽的缓冲层薄。 实施干蚀刻工艺以使与较宽和较窄缓冲层相对应的衬底形成多个沟槽。 当蚀刻较宽和较窄的缓冲层时，首先去除较窄的缓冲层，使得对应于较窄缓冲层的衬底将比对应于较宽缓冲层的衬底早蚀刻。

公开(公告)号：US08309998B2

公开(公告)日：2012-11-13

申请号：US13102039

申请日：2011-05-05

申请人： Tzung-Han Lee ,  Chung-Yuan Lee

发明人： Tzung-Han Lee ,  Chung-Yuan Lee

IPC分类号： H01L27/108

CPC分类号： H01L29/7841 ,  H01L27/10802 ,  H01L29/66666 ,  H01L29/7827

摘要： A memory structure having a floating body is provided, which includes a substrate including an active area and an isolation structure surrounding the active area, a first source/drain region in the substrate in the active area, a first floating body in the substrate above the first source/drain region, a second floating body on the first floating body, a second source/drain region on the second floating body, and a trench-type gate structure in the substrate and beside the first floating body. A method of fabricating a memory structure having a floating body is also provided.

摘要翻译： 提供一种具有浮体的存储器结构，其包括：衬底，其包括有源区域和围绕有源区域的隔离结构;有源区域中的衬底中的第一源极/漏极区域;位于衬底中的第一浮置体 第一源极/漏极区域，第一浮体上的第二浮体，第二浮体上的第二源极/漏极区域，以及衬底中的沟槽型栅极结构以及第一浮体旁边。 还提供了一种制造具有浮体的存储结构的方法。

公开(公告)号：US20110260230A1

公开(公告)日：2011-10-27

申请号：US12829674

申请日：2010-07-02

申请人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  HSIEN-WEN LIU

发明人： TZUNG HAN LEE ,  CHUNG-LIN HUANG ,  HSIEN-WEN LIU

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10891 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： A memory cell with surrounding word line structures includes an active area; a plurality of first trenches formed on the active area in a first direction, each first trench has a bit line on a sidewall therein; a plurality of second trenches formed on the active area in a second direction, each second trench has two word lines formed correspondingly on the sidewalls in the second trench; and a plurality of transistors formed on the active area. The word line pairs are arranged into a surrounding word line structure. The transistor is controlled by the bit line and the two word lines, thus improving the speed of the transistor.

摘要翻译： 具有周围字线结构的存储单元包括有源区; 在第一方向上形成在有源区上的多个第一沟槽，每个第一沟槽在其侧壁上具有位线; 在第二方向上形成在有源区上的多个第二沟槽，每个第二沟槽具有相应地形成在第二沟槽中的侧壁上的两条字线; 以及形成在有源区上的多个晶体管。 字线对被排列成周围的字线结构。 晶体管由位线和两个字线控制，从而提高晶体管的速度。

公开(公告)号：US07960241B2

公开(公告)日：2011-06-14

申请号：US12698322

申请日：2010-02-02

申请人： Shin-Bin Huang ,  Tzung-Han Lee ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Tzung-Han Lee ,  Chung-Lin Huang

IPC分类号： H01L21/20

CPC分类号： H01L27/10852 ,  H01L28/90

摘要： A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors.

摘要翻译： 堆叠DRAM的双面电容器的制造方法具有以下步骤：在隔离沟槽和电容器沟槽中形成牺牲结构; 在所述牺牲结构上形成第一覆盖层和第二覆盖层; 修改第二覆盖层的一部分; 去除未改性的第二覆盖层和第一覆盖层以暴露牺牲结构; 去除所述牺牲结构的暴露部分以暴露所述电极层; 去除暴露的电极层以暴露氧化物层; 并去除氧化物层和牺牲结构以形成双面电容器。

公开(公告)号：US20110053337A1

公开(公告)日：2011-03-03

申请号：US12827082

申请日：2010-06-30

申请人： CHIEN-HSUN CHEN ,  TZUNG HAN LEE ,  CHUNG-LIN HUANG

发明人： CHIEN-HSUN CHEN ,  TZUNG HAN LEE ,  CHUNG-LIN HUANG

IPC分类号： H01L21/762

CPC分类号： H01L27/10876 ,  H01L21/76224 ,  H01L27/10894

摘要： A self-alignment method for a recess channel dynamic random access memory includes providing a substrate with a target layer, a barrier layer and a lining layer, wherein the target layer has shallow trench isolation structures; patternizing the lining layer, barrier layer and target layer to form recess trench channels; depositing a dielectric layer onto the recess trench channel; forming an ion doped region in the target layer; removing a portion of the dielectric layer to expose a portion of the recess trench channel; forming a filler layer covered onto the recess trench channel; removing a portion of the filler layer to expose a portion of the recess trench channel; forming a passivation layer onto the recess trench channel; removing the passivation layer on the lining layer; and removing the lining layer to form a plurality of structural monomers disposed at the recess trench channel and protruded from the target layer.

摘要翻译： 用于凹槽通道动态随机存取存储器的自对准方法包括：提供具有目标层，阻挡层和衬里层的衬底，其中所述目标层具有浅沟槽隔离结构; 图案化衬里层，阻挡层和目标层以形成凹槽沟道; 将介电层沉积到凹槽沟道上; 在靶层中形成离子掺杂区; 去除所述电介质层的一部分以暴露所述凹槽沟槽沟道的一部分; 形成覆盖在所述凹槽沟道上的填充层; 去除所述填充层的一部分以暴露所述凹槽沟道的一部分; 在所述凹槽沟道上形成钝化层; 去除衬里层上的钝化层; 并且移除所述衬里层以形成设置在所述凹槽沟道处并从所述目标层突出的多个结构单体。