公开(公告)号：US08158475B2

公开(公告)日：2012-04-17

申请号：US12879777

申请日：2010-09-10

申请人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

摘要翻译： 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。 栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。 第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

公开(公告)号：US08125550B2

公开(公告)日：2012-02-28

申请号：US12209199

申请日：2008-09-11

申请人： Tsung-Yi Su ,  Han-Chi Liu

发明人： Tsung-Yi Su ,  Han-Chi Liu

IPC分类号： H04N3/14 ,  H04N5/335 ,  H03N1/12

CPC分类号： H04N5/3575 ,  H04N5/374

摘要： A correlation double sampling (CDS) circuit for sampling a reset signal and a light-sensing signal outputted from a pixel column of an image sensor includes two sampling capacitors and four transistor switches. The operation of the CDS circuit needs not change polarities of the two sampling capacitors, such that MOS capacitors that have higher capacitance per unit area can be utilized for realizing the two sampling capacitors for reducing thermal noises induced when performing sampling. Additionally, fewer transistors are used in the CDS circuit, and thus charge injection noises caused by switching the transistor switches can also be reduced.

摘要翻译： 用于对复位信号进行采样的相关双采样（CDS）电路和从图像传感器的像素列输出的感光信号包括两个采样电容器和四个晶体管开关。 CDS电路的操作不需要改变两个采样电容器的极性，使得具有较高每单位面积电容的MOS电容器可用于实现两个采样电容器，以减少在执行采样时引起的热噪声。 此外，在CDS电路中使用更少的晶体管，因此也可以减少由开关晶体管开关引起的电荷注入噪声。

公开(公告)号：US20110059359A1

公开(公告)日：2011-03-10

申请号：US12862803

申请日：2010-08-25

申请人： Hung-Chun WU ,  Ching-Yi Su ,  Ping-Hsun Hsieh ,  Bing-Ming Lin ,  Mo-Hua Yang ,  Nae-Lih Wu

发明人： Hung-Chun WU ,  Ching-Yi Su ,  Ping-Hsun Hsieh ,  Bing-Ming Lin ,  Mo-Hua Yang ,  Nae-Lih Wu

IPC分类号： H01M4/36 ,  H01M4/505 ,  H01M4/52

CPC分类号： H01M10/052 ,  H01M4/525 ,  H01M4/5825 ,  H01M2004/021 ,  H01M2004/028

摘要： A lithium ion secondary battery includes LiFePO4 as a major component of the positive electrode active material. In order to implement the high rate capability with 10 C/1 C rate larger than 80%, the invention designs a positive electrode on a current collector with a ratio (A/t) of coating area to coating thickness greater than 1.2×106 (mm) and uses more than one tab on the current collector. The design of the invention can be applied to other active materials with low conductivity as the positive electrode for lithium ion battery.

摘要翻译： 锂离子二次电池包括作为正极活性物质的主要成分的LiFePO 4。 为了实现大于80％的10 C / 1 C的高速率能力，本发明在集电器上设计了一个正电极，涂层面积与涂层厚度之比（A / t）大于1.2×106（ mm），并在集电器上使用多个选项卡。 本发明的设计可以应用于其他具有低导电性的活性材料作为锂离子电池的正极。

公开(公告)号：US20110008944A1

公开(公告)日：2011-01-13

申请号：US12879777

申请日：2010-09-10

申请人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

摘要翻译： 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。 栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。 第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

公开(公告)号：USD625699S1

公开(公告)日：2010-10-19

申请号：US29347599

申请日：2010-03-11

申请人： Peng-Yu Huang ,  Shiou-Yi Su ,  Ming-Chih Chien ,  Chih-Tsang Yeh

设计人： Peng-Yu Huang ,  Shiou-Yi Su ,  Ming-Chih Chien ,  Chih-Tsang Yeh

公开(公告)号：US20100259467A1

公开(公告)日：2010-10-14

申请号：US12758123

申请日：2010-04-12

申请人： Tsung-Yi Su ,  Yu-Hung Dai ,  Chang-Ho Tseng

发明人： Tsung-Yi Su ,  Yu-Hung Dai ,  Chang-Ho Tseng

IPC分类号： G09G3/30

CPC分类号： H01L27/3246 ,  H01L27/3258 ,  H01L27/3276 ,  H01L51/5203 ,  H05B33/06

摘要： An embodiment of the invention provides a display panel, which includes a substrate having a pixel region and a peripheral region, a control element overlying the pixel region of the substrate, a conducting layer overlying the substrate in the peripheral region, a first insulating layer overlying the conducting layer in the peripheral region, wherein a ratio between an area of the first insulating layer and an area of the conducting layer in the peripheral region is between about 0.27 and 0.99, a lower electrode layer overlying the first insulating layer, and a second insulating layer overlying the lower electrode layer.

摘要翻译： 本发明的实施例提供了一种显示面板，其包括具有像素区域和外围区域的基板，覆盖基板的像素区域的控制元件，覆盖在周边区域中的基板的导电层，覆盖在第一绝缘层 所述周边区域中的导电层，其中所述第一绝缘层的面积与所述外围区域中的所述导电层的面积之间的比率在约0.27和0.99之间，覆盖所述第一绝缘层的下电极层和第二绝缘层 绝缘层覆盖下电极层。

公开(公告)号：US07672350B2

公开(公告)日：2010-03-02

申请号：US12164923

申请日：2008-06-30

申请人： Chen Ji ,  Chung-Yi Su

发明人： Chen Ji ,  Chung-Yi Su

IPC分类号： H01S5/00

CPC分类号： H01S5/1021 ,  H01S5/0658 ,  H01S5/1092 ,  H01S5/18358

摘要： A semiconductor device is provided that includes an optical feedback structure that is monolithically integrated with a VCSEL device and which extends the speed of the VCSEL device beyond the speed to which it would otherwise be limited due to relaxation oscillation. The optical feedback structure does not rely on light emissions from the VCSEL substrate material to produce optical feedback. Consequently, extension of the bandwidth of the semiconductor device through the use of optical feedback is not limited by the absorption threshold wavelength of the substrate material. Furthermore, because the optical feedback structure does not include the substrate, the ability to use optical feedback to extend the bandwidth of the device is independent of the precision with which the substrate thickness can be controlled.

摘要翻译： 提供了一种半导体器件，其包括与VCSEL器件单片集成的光学反馈结构，并且将VCSEL器件的速度延伸超过由于弛豫振荡否则将被限制的速度。 光学反馈结构不依赖于来自VCSEL衬底材料的光发射以产生光学反馈。 因此，通过使用光学反馈来扩展半导体器件的带宽不受衬底材料的吸收阈值波长的限制。 此外，由于光学反馈结构不包括衬底，所以使用光学反馈来扩展器件的带宽的能力与可以控制衬底厚度的精度无关。

公开(公告)号：US20100025255A1

公开(公告)日：2010-02-04

申请号：US12498455

申请日：2009-07-07

申请人： JONG-YI SU ,  CHENG-SHIN CHEN ,  REN-NING WANG ,  HONG-JUN QU

发明人： JONG-YI SU ,  CHENG-SHIN CHEN ,  REN-NING WANG ,  HONG-JUN QU

IPC分类号： C25D5/10

CPC分类号： C23C18/36 ,  C23C18/1653 ,  C23C18/1844 ,  C25D3/06 ,  C25D3/12 ,  C25D3/38 ,  C25D5/14 ,  C25D5/42 ,  C25D5/48

摘要： An electroplating method for magnesium and magnesium alloys, comprising: providing a magnesium or magnesium alloy substrate and pre-treating it to be cleaned; roughening the surface of the substrate; activating the surface of the substrate; chemically plating the substrate to form a nickel coating on its surface; and electroplating the substrate to form, in order, a first nickel coating, a copper coating, a second nickel coating, and a chromium coating on the chemically produced nickel coating.

摘要翻译： 一种用于镁和镁合金的电镀方法，包括：提供镁或镁合金基底并预处理待清洁; 粗糙化基材的表面; 激活基板的表面; 化学镀基板以在其表面上形成镍涂层; 以及对该基板进行电镀，以依次形成化学生产的镍涂层上的第一镍涂层，铜涂层，第二镍涂层和铬涂层。

公开(公告)号：US20100006934A1

公开(公告)日：2010-01-14

申请号：US12170133

申请日：2008-07-09

申请人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

摘要翻译： 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。 栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。 第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

公开(公告)号：US20090323751A1

公开(公告)日：2009-12-31

申请号：US12164923

申请日：2008-06-30

申请人： Chen Ji ,  Chung-Yi Su

发明人： Chen Ji ,  Chung-Yi Su

IPC分类号： H01S5/183 ,  H01S5/026

CPC分类号： H01S5/1021 ,  H01S5/0658 ,  H01S5/1092 ,  H01S5/18358

摘要： A semiconductor device is provided that includes an optical feedback structure that is monolithically integrated with a VCSEL device and which extends the speed of the VCSEL device beyond the speed to which it would otherwise be limited due to relaxation oscillation. The optical feedback structure does not rely on light emissions from the VCSEL substrate material to produce optical feedback. Consequently, extension of the bandwidth of the semiconductor device through the use of optical feedback is not limited by the absorption threshold wavelength of the substrate material. Furthermore, because the optical feedback structure does not include the substrate, the ability to use optical feedback to extend the bandwidth of the device is independent of the precision with which the substrate thickness can be controlled.

摘要翻译： 提供了一种半导体器件，其包括与VCSEL器件单片集成的光学反馈结构，并且将VCSEL器件的速度延伸超过由于弛豫振荡否则将被限制的速度。 光学反馈结构不依赖于来自VCSEL衬底材料的光发射以产生光学反馈。 因此，通过使用光学反馈来扩展半导体器件的带宽不受衬底材料的吸收阈值波长的限制。 此外，由于光学反馈结构不包括衬底，所以使用光学反馈来扩展器件的带宽的能力与可以控制衬底厚度的精度无关。