公开(公告)号：US20160196065A1

公开(公告)日：2016-07-07

申请号：US14588947

申请日：2015-01-04

Applicant: APPLE INC.

Inventor： Shai Ojalvo ,  Eyal Gurgi ,  Yoav Kasorla

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7207 ,  G06F2212/7208

Abstract: A method includes, in a memory system that includes multiple memory units, holding information indicative of respective programming durations of the memory units. Data is stored in a stripe that includes a plurality of the memory units, by programming the memory units in the stripe in an order that is set based on the information.

Abstract translation: 一种方法包括在包括多个存储器单元的存储器系统中，保存指示存储器单元的相应编程持续时间的信息。 通过以基于该信息设置的顺序对条带中的存储器单元进行编程，将数据存储在包括多个存储器单元的条带中。

公开(公告)号：US09263135B2

公开(公告)日：2016-02-16

申请号：US13804427

申请日：2013-03-14

Applicant: Apple Inc.

Inventor： Yoav Kasorla ,  Avraham Poza Meir ,  Eyal Gurgi

IPC: G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3427

Abstract: A method includes providing data for storage in a memory, which includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines, and a third dimension associated with sections. The data is stored in the memory cells in accordance with a programming order that alternates among the sections, including storing a first portion of the data in a first section, then storing a second portion of the data in a second section different from the first section, and then storing a third portion of the data in the first section.

Abstract translation: 一种方法包括提供用于存储在存储器中的数据，其包括以具有与位线相关联的第一维度的三维（3-D）配置布置的多个模拟存储器单元，与字线相关联的第二维度，以及第三维度 与部分相关联。 根据在这些部分之间交替的编程顺序将数据存储在存储器单元中，包括在第一部分中存储数据的第一部分，然后将数据的第二部分存储在与第一部分不同的第二部分中 ，然后将数据的第三部分存储在第一部分中。

公开(公告)号：US09262315B2

公开(公告)日：2016-02-16

申请号：US13935746

申请日：2013-07-05

Applicant: Apple Inc.

Inventor： Avraham Poza Meir ,  Eyal Gurgi ,  Shai Ojalvo ,  Yoav Kasorla ,  Naftali Sommer

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7211

Abstract: A method for data storage in a memory that includes multiple analog memory cells, includes defining, based on a characteristic of the memory cells, an uneven wear leveling scheme that programs and erases at least first and second subsets of the memory cells with respective different first and second Programming and Erasure (P/E) rates. Data is stored in the memory in accordance with the uneven wear leveling scheme.

Abstract translation: 一种用于在包括多个模拟存储器单元的存储器中的数据存储的方法，包括基于所述存储器单元的特性定义不均匀磨损平衡方案，所述不均匀磨损均衡方案以相应不同的第一方式来编程和擦除所述存储器单元的至少第一和第二子集 和第二个编程和擦除（P / E）率。 根据不均匀的磨损均衡方案将数据存储在存储器中。

公开(公告)号：US20150348645A1

公开(公告)日：2015-12-03

申请号：US14821254

申请日：2015-08-07

Applicant: Apple Inc.

Inventor： Yoav Kasorla ,  Shai Ojalvo ,  Eyal Gurgi

IPC: G11C17/18 ,  G06F11/10 ,  G11C17/16

CPC classification number: G11C17/18 ,  G06F11/1044 ,  G11C17/16 ,  G11C29/74 ,  G11C29/787

Abstract: An integrated circuit includes fuse readout logic and first and second sets of fuses. One of the sets includes one or more primary fuses whose burn states represent respective bit values, and the other of the sets includes one or more secondary fuses whose burn states are indicative of the bit values stored in the primary fuses. The fuse readout logic is configured to read the bit values by sensing the burn states of the primary fuses, and to conditionally correct the read bit values by sensing the burn states of one or more of the secondary fuses.

Abstract translation: 集成电路包括熔丝读出逻辑和第一和第二组保险丝。 其中一个集合包括一个或多个主熔丝，其燃烧状态表示相应的位值，并且这些组中的另一个包括一个或多个辅助熔丝，其燃烧状态指示存储在主熔丝中的位值。 熔丝读出逻辑被配置为通过感测主熔丝的燃烧状态来读取位值，并且通过感测一个或多个次熔丝的燃烧状态来有条件地校正读取位值。

公开(公告)号：US09136003B1

公开(公告)日：2015-09-15

申请号：US14249403

申请日：2014-04-10

Applicant: Apple Inc.

Inventor： Avraham Poza Meir ,  Eyal Gurgi ,  Naftali Sommer ,  Yoav Kasorla

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/3418 ,  G11C16/3427

Abstract: A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group.

Abstract translation: 一种方法包括在共享公共隔离层并存储在公共隔离层中的代表数据值的电荷量的多个存储器单元中，分配用于数据存储的第一组存储器单元，以及分配第二组 用于保护存储在第一组中的电荷的存储单元不保持漂移。 数据存储在第一组的存储单元中。 防止第一组的存储单元中保持漂移的电荷的保护量被存储在第二组的存储单元中。

公开(公告)号：US09135113B2

公开(公告)日：2015-09-15

申请号：US14048492

申请日：2013-10-08

Applicant: Apple Inc.

Inventor： Shai Ojalvo ,  Eyal Gurgi ,  Yoav Kasorla

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0683 ,  G06F11/008 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1076 ,  G11C29/52

Abstract: A method includes storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data in a volatile buffer and then writing the buffered data to the analog memory cells while overwriting at least some of the data in the volatile buffer with success indications. Upon detecting a failure in writing the buffered data to the analog memory cells, recovered data is produced by reading both the volatile buffer and the analog memory cells, assigning reliability metrics to respective bits of the recovered data depending on whether the bits were read from the volatile buffer or from the analog memory cells, applying ECC decoding to the recovered data using the reliability metrics and reprogramming the recovered data.

Abstract translation: 一种方法包括通过将数据缓冲在易失性缓冲器中来将数据编码的纠错码（ECC）存储在模拟存储器单元中，然后将缓冲的数据写入模拟存储器单元，同时重写易失性缓冲器中的至少一些数据 有成功迹象。 在检测到将缓冲数据写入模拟存储器单元的故障时，通过读取易失性缓冲器和模拟存储器单元来产生恢复的数据，根据是否从 易失性缓冲器或模拟存储器单元，使用可靠性度量将ECC解码应用于恢复的数据，并重新编程恢复的数据。

公开(公告)号：US20150227440A1

公开(公告)日：2015-08-13

申请号：US14178668

申请日：2014-02-12

Applicant: Apple Inc.

Inventor： Shai Ojalvo ,  Eyal Gurgi ,  Yoav Kasorla

IPC: G06F11/16

CPC classification number: G06F11/1604 ,  G06F13/00 ,  G06F13/4086 ,  H03K19/0005

Abstract: A method includes communicating over an interface between a controller and multiple memory dies, which comprise respective on-die terminations (ODTs) that are each connectable to the interface by the controller. A plurality of termination settings are evaluated, each termination setting specifies a respective subset of the ODTs to be connected to the interface, so as to identify a preferred termination setting in which the communication quality with a given memory die meets a predefined criterion. Subsequent communication with the given memory die is performed while applying the preferred termination setting.

Abstract translation: 一种方法包括通过控制器和多个存储器管芯之间的接口进行通信，所述存储器管芯包括各自的管芯端子（ODT），每个管芯端子可由控制器连接到接口。 评估多个终止设置，每个终止设置指定要连接到接口的ODT的相应子集，以便识别与给定存储器管芯的通信质量符合预定标准的优选终止设置。 在应用优选的终止设置的同时执行与给定存储器管芯的后续通信。

公开(公告)号：US09105311B2

公开(公告)日：2015-08-11

申请号：US14332650

申请日：2014-07-16

Applicant: Apple Inc.

Inventor： Yael Shur ,  Yoav Kasorla ,  Eyal Gurgi

IPC: G11C7/22 ,  G11C7/00 ,  G11C13/00 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C27/00

CPC classification number: G11C7/00 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C27/005

Abstract: A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed.

Abstract translation: 一种方法包括选择用于在与相应字线相关联的行中排列的模拟存储器单元阵列中编程的字线，所述行与相应位线相关联。 将所选字线中的存储单元编程的字线电压施加到相应的字线。 将所选择的字线外部的一个或多个附加存储单元作为所选字线编程的结果编程的位线电压被施加到相应的位线。 使用所应用的字线和位线电压，将数据存储在所选字线中的存储单元中，并且附加存储单元被同时编程。

公开(公告)号：US09021334B2

公开(公告)日：2015-04-28

申请号：US13874995

申请日：2013-05-01

Applicant: Apple Inc.

Inventor： Barak Baum ,  Tomer Ish-Shalom ,  Micha Anholt ,  Eyal Gurgi ,  Yoav Kasorla

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1076 ,  G11C7/14 ,  G11C11/5621 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42

Abstract: A method includes, in a memory that includes two or more memory units, storing a code word of an Error Correction Code (ECC) that is representable by a plurality of check equations, such that a first part of the code word is stored in a first memory unit and a second part of the code word is stored in a second memory unit. A subset of the check equations, which operate only on code word bits belonging to the first part stored in the first memory unit, is identified. The first part of the code word is retrieved from the first memory unit, and a count of the check equations in the identified subset that are not satisfied by the retrieved first part of the code word is evaluated. One or more readout parameters, for readout from the first memory unit, are set depending on the evaluated count.

Abstract translation: 一种方法包括在包括两个或多个存储器单元的存储器中，存储可由多个检验方程表示的纠错码（ECC）的代码字，使得代码字的第一部分被存储在 第一存储单元和码字的第二部分被存储在第二存储单元中。 识别仅对属于存储在第一存储器单元中的第一部分的代码字位操作的检验方程的子集。 从第一存储器单元检索代码字的第一部分，并且对所检索的代码字的第一部分不满足的所识别的子集中的检验方程的计数进行评估。 根据评估计数来设定用于从第一存储器单元读出的一个或多个读出参数。

公开(公告)号：US09007835B2

公开(公告)日：2015-04-14

申请号：US13865351

申请日：2013-04-18

Applicant: Apple Inc.

Inventor： Avraham Poza Meir ,  Eyal Gurgi ,  Naftali Sommer ,  Yoav Kasorla

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

Abstract: A method includes storing data in a memory, which includes multiple strings of analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines and a third dimension associated with sections, such that each string is associated with a respective bit line and a respective section and includes multiple memory cells that are connected to the respective word lines. For a group of the strings, respective values of a property of the strings in the group are evaluated. Source-side voltages are calculated for the respective strings in the group, depending on the respective values of the property, and respective source-sides of the strings in the group are biased with the corresponding source-side voltages. A memory operation is performed on the strings in the group while the strings are biased with the respective source-side voltages.

Abstract translation: 一种方法包括将数据存储在存储器中，其包括以具有与位线相关联的第一维度的三维（3-D）配置布置的多个模拟存储器单元串，与字线相关联的第二维度和与第三维度相关联的第三维度 具有部分，使得每个字符串与相应的位线和相应的部分相关联，并且包括连接到各个字线的多个存储器单元。 对于一组字符串，对组中字符串的属性的各个值进行评估。 根据属性的各个值，针对组中的各个串来计算源侧电压，并且组中的串的各个源侧被相应的源极侧电压偏置。 当串被相应的源侧电压偏置时，对组中的串执行存储器操作。