公开(公告)号：US06482688B2

公开(公告)日：2002-11-19

申请号：US09822998

申请日：2001-03-30

Applicant: Chimin Hu ,  Amitabh Jain ,  Reima Tapani Laaksonen ,  Manoj Mehrotra

Inventor： Chimin Hu ,  Amitabh Jain ,  Reima Tapani Laaksonen ,  Manoj Mehrotra

IPC: H01L21338

CPC classification number: H01L21/28114 ,  H01L21/28123

Abstract: A method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises selectively etching the poly/amorphous silicon layer stack, wherein an etch rate associated with the generally amorphous silicon layer in an over etch step associated therewith is less than an etch rate associated with the polysilicon layer, thereby causing a lateral portion of the generally amorphous silicon layer to extend beyond a corresponding lateral portion of the polysilicon layer.

Abstract translation: 形成大致T形结构的方法。 该方法包括形成多晶硅层堆叠，其包括多晶硅层和覆盖多晶硅层的大致非晶硅层。 该方法还包括选择性地蚀刻多晶硅/非晶硅层堆叠，其中在与其相关的过蚀刻步骤中与一般非晶硅层相关联的蚀刻速率小于与多晶硅层相关的蚀刻速率，从而导致 通常非晶硅层延伸超过多晶硅层的对应横向部分。

公开(公告)号：US08691644B2

公开(公告)日：2014-04-08

申请号：US13541957

申请日：2012-07-05

Applicant: Seung-Chul Song ,  Amitabh Jain ,  Deborah J. Riley

Inventor： Seung-Chul Song ,  Amitabh Jain ,  Deborah J. Riley

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.

Abstract translation: 形成应力通道NMOS晶体管和应变通道PMOS晶体管的方法在植入n型源极和漏极掺杂剂之前形成p型源极和漏极区，并且形成应力记忆层，由此减小施加到n - 沟道的PMOS晶体管。 此外，在形成p型源极和漏极区之后，但在植入n型掺杂剂之前，形成非导电层。 不导电层允许实现较浅的n型植入物，并且还用作应力记忆层的缓冲层。

公开(公告)号：US08558310B2

公开(公告)日：2013-10-15

申请号：US12967105

申请日：2010-12-14

Applicant: Mahalingam Nandakumar ,  Amitabh Jain

Inventor： Mahalingam Nandakumar ,  Amitabh Jain

IPC: H01L21/02 ,  H01L21/8234

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/66477 ,  H01L29/7833

Abstract: A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.

公开(公告)号：US20130009251A1

公开(公告)日：2013-01-10

申请号：US13484592

申请日：2012-05-31

Applicant: Amitabh Jain

Inventor： Amitabh Jain

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/66 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process of integrated circuit manufacturing includes providing (32, 33) a spacer on a gate stack to provide a horizontal offset over the channel region for otherwise-direct application (34) of a PLDD implant dose in semiconductor, additionally depositing (35) a seal substance to provide a screen thickness vertically while thereby augmenting the spacer on the gate stack to provide an increased offset horizontally from the gate stack and form a horizontal screen free of etch, and subsequently providing (36) an NLDD implant dose for NLDD formation. Various integrated circuit structures, devices, and other processes of manufacture, and processes of testing are also disclosed.

Abstract translation: 集成电路制造的过程包括在栅极叠层上提供（32,33）间隔物，以在沟道区域上提供水平偏移，用于在半导体中另外存储（35）一个PLDD注入剂量的直接应用（34） 密封物质以垂直地提供屏幕厚度，从而增加栅极堆叠上的间隔物，以提供与栅极堆叠水平的增加的偏移，并形成没有蚀刻的水平屏幕，并且随后提供（36）用于NLDD形成的NLDD注入剂量。 还公开了各种集成电路结构，装置和其它制造工艺以及测试过程。

公开(公告)号：US08253205B2

公开(公告)日：2012-08-28

申请号：US13016393

申请日：2011-01-28

Applicant: Amitabh Jain

Inventor： Amitabh Jain

IPC: H01L21/70

CPC classification number: H01L21/26506 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/26593 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/7848

Abstract: An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ≦1010 dislocation lines/cm2 and an active concentration of the compressive strain inducing specie that is above a solid solubility limit for the compressive strain inducing specie in the compressive strain inducing region. A method for forming compressively strained PMOS transistors includes implanting on at least opposing sides of the gate stack using at least one compressive strain inducing specie selected from Ge, Sn and Pb at a dose ≧1×1015 cm−2, at an implantation temperature during implanting in a temperature range ≦273 K, wherein the implant conditions are sufficient to form an amorphous region. The wafer is annealed using annealing conditions including a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at the peak temperature of ≦10 seconds, wherein the amorphous region recrystallizes by solid phase epitaxy (SPE).

Abstract translation: 集成电路（IC）包括多个压缩应变PMOS晶体管。 IC包括具有半导体表面的衬底。 栅堆叠形成在半导体表面中或半导体表面上，并且在栅极电介质上包括栅电极，其中沟道区位于栅电介质下方的半导体表面中。 源极和漏极区域是栅极堆叠的相对侧。 包括至少一种选自Ge，Sn和Pb的物质的至少一个压缩应变诱导区域位于PMOS晶体管的源极和漏极区域的至少一部分中，其中应变诱导区域提供1010个位错线/ cm 2 以及压缩应变诱导物质的活性浓度高于在压缩应变诱导区域中的压缩应变诱导物质的固溶度极限。 用于形成压缩应变PMOS晶体管的方法包括：在植入温度期间，使用至少一种压应变诱导物质，以剂量≥1×1015cm-2，在栅极堆叠的至少相对侧上注入; 在温度范围内注入; 273K，其中注入条件足以形成非晶区域。 使用包括1050℃至1400℃的峰退火温度和在峰值温度为＆lt; lE; 10秒的退火时间的退火条件对晶片进行退火，其中非晶区域通过固相外延（SPE）重结晶。

公开(公告)号：US08216945B2

公开(公告)日：2012-07-10

申请号：US12757665

申请日：2010-04-09

Applicant: Steven L. Prins ,  Brian K. Kirkpatrick ,  Amitabh Jain

Inventor： Steven L. Prins ,  Brian K. Kirkpatrick ,  Amitabh Jain

IPC: H01L21/311 ,  H01L21/469 ,  H01L21/31

CPC classification number: H01L22/20 ,  G03F7/70616 ,  G03F7/70783 ,  G03F7/70875 ,  H01L22/12

Abstract: A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present.

Abstract translation: 一种用于在光刻图案级别之间控制晶片的平坦度的方法。 在晶片的顶侧半导体表面上进行第一光刻步骤。 获得晶片的参考曲率信息。 参考曲率不是平面的。 执行至少一个处理步骤，其导致相对于参考曲率改变的曲率。 获得用于晶片的变化的曲率信息。 修改了晶片底部表面上的应力，减小了改变的曲率和参考曲率之间的差异。 在存在改性应力分布的同时，在顶侧半导体表面上进行第二光刻步骤。

公开(公告)号：US08125035B2

公开(公告)日：2012-02-28

申请号：US12696215

申请日：2010-01-29

Applicant: Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

Inventor： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1087 ,  H01L29/7847

Abstract: Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

Abstract translation: 对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。 本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。 实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。 来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

公开(公告)号：US20110312168A1

公开(公告)日：2011-12-22

申请号：US13217577

申请日：2011-08-25

Applicant: Amitabh Jain

Inventor： Amitabh Jain

IPC: H01L21/225

CPC classification number: H01L21/823814 ,  H01L21/2251 ,  H01L21/2255 ,  H01L21/26566 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/84 ,  H01L29/6659 ,  H01L29/7833

Abstract: A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm−2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the IC substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both NLDD and PLDD regions.

Abstract translation: 公开了一种用于在IC衬底，特别是MOS晶体管中的LDD区域形成平均掺杂剂量高于1014cm -2的深度小于20nm的扩散区域的工艺。 使用气体簇离子束（GCIB）注入，分子离子注入或原子离子注入将掺杂剂注入到源电介质层中，导致IC衬底中的可忽略的损伤。 尖峰退火或激光退火将注入的掺杂剂扩散到IC衬底中。 本发明的方法也可以应用于形成源极和漏极（S / D）区域。 一个源介质层可用于形成NLDD和PLDD区域。

公开(公告)号：US08026135B2

公开(公告)日：2011-09-27

申请号：US12190337

申请日：2008-08-12

Applicant: Amitabh Jain

Inventor： Amitabh Jain

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/2251 ,  H01L21/2255 ,  H01L21/26566 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/84 ,  H01L29/6659 ,  H01L29/7833

Abstract: A process for forming diffused region less than 20 nanometers deep with an average doping dose above 1014 cm−2 in an IC substrate, particularly LDD region in an MOS transistor, is disclosed. Dopants are implanted into a source dielectric layer using gas cluster ion beam (GCIB) implantation, molecular ion implantation or atomic ion implantation resulting in negligible damage in the IC substrate. A spike anneal or a laser anneal diffuses the implanted dopants into the IC substrate. The inventive process may also be applied to forming source and drain (S/D) regions. One source dielectric layer may be used for forming both NLDD and PLDD regions.

Abstract translation: 公开了一种用于在IC衬底，特别是MOS晶体管中的LDD区域形成平均掺杂剂量高于1014cm -2的深度小于20nm的扩散区域的工艺。 使用气体簇离子束（GCIB）注入，分子离子注入或原子离子注入将掺杂剂注入到源电介质层中，导致IC衬底中的可忽略的损伤。 尖峰退火或激光退火将注入的掺杂剂扩散到IC衬底中。 本发明的方法也可以应用于形成源极和漏极（S / D）区域。 一个源介质层可用于形成NLDD和PLDD区域。

公开(公告)号：US20110147854A1

公开(公告)日：2011-06-23

申请号：US12967105

申请日：2010-12-14

Applicant: Mahalingam Nandakumar ,  Amitabh Jain

Inventor： Mahalingam Nandakumar ,  Amitabh Jain

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/66477 ,  H01L29/7833

Abstract: A method of forming an integrated circuit (IC) having at least one PMOS transistor includes performing PLDD implantation including co-implanting indium, carbon and a halogen, and a boron specie to establish source/drain extension regions in a substrate having a semiconductor surface on either side of a gate structure including a gate electrode on a gate dielectric formed on the semiconductor surface. Source and drain implantation is performed to establish source/drain regions, wherein the source/drain regions are distanced from the gate structure further than the source/drain extension regions. Source/drain annealing is performed after the source and drain implantation. The co-implants can be selectively provided to only core PMOS transistors, and the method can include a ultra high temperature anneal such as a laser anneal after the PLDD implantation.

Abstract translation: 形成具有至少一个PMOS晶体管的集成电路（IC）的方法包括执行PLDD注入，包括共注入铟，碳和卤素，以及硼物种，以在具有半导体表面的衬底中建立源极/漏极延伸区域 栅极结构的任一侧包括形成在半导体表面上的栅极电介质上的栅电极。 进行源极和漏极注入以建立源极/漏极区域，其中源极/漏极区域远离源极/漏极延伸区域远离栅极结构。 在源极和漏极注入之后进行源极/漏极退火。 共注入物可以选择性地仅提供到核心PMOS晶体管，并且该方法可以包括超高温退火，例如在PLDD注入之后的激光退火。