公开(公告)号：US06482688B2

公开(公告)日：2002-11-19

申请号：US09822998

申请日：2001-03-30

申请人： Chimin Hu ,  Amitabh Jain ,  Reima Tapani Laaksonen ,  Manoj Mehrotra

发明人： Chimin Hu ,  Amitabh Jain ,  Reima Tapani Laaksonen ,  Manoj Mehrotra

IPC分类号： H01L21338

CPC分类号： H01L21/28114 ,  H01L21/28123

摘要： A method of forming a generally T-shaped structure. The method comprises forming a poly/amorphous silicon layer stack which comprises a polysilicon layer and a generally amorphous silicon layer overlying the polysilicon layer. The method further comprises selectively etching the poly/amorphous silicon layer stack, wherein an etch rate associated with the generally amorphous silicon layer in an over etch step associated therewith is less than an etch rate associated with the polysilicon layer, thereby causing a lateral portion of the generally amorphous silicon layer to extend beyond a corresponding lateral portion of the polysilicon layer.

摘要翻译： 形成大致T形结构的方法。 该方法包括形成多晶硅层堆叠，其包括多晶硅层和覆盖多晶硅层的大致非晶硅层。 该方法还包括选择性地蚀刻多晶硅/非晶硅层堆叠，其中在与其相关的过蚀刻步骤中与一般非晶硅层相关联的蚀刻速率小于与多晶硅层相关的蚀刻速率，从而导致 通常非晶硅层延伸超过多晶硅层的对应横向部分。

公开(公告)号：US07670917B2

公开(公告)日：2010-03-02

申请号：US11853328

申请日：2007-09-11

申请人： Amitabh Jain ,  Manoj Mehrotra

发明人： Amitabh Jain ,  Manoj Mehrotra

IPC分类号： H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28044 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845

摘要： In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal.

摘要翻译： 在一个方面，提供一种制造半导体器件的方法，包括在半导体衬底上形成栅电极，在栅电极附近形成源极/漏极，在栅电极上沉积应力诱导层。 在至少约1100℃的温度下沉积应力诱导层至少约300微秒的时间之后，至少在栅电极上进行激光退火，并且半导体器件经受热 在进行激光退火之后退火。

公开(公告)号：US07615458B2

公开(公告)日：2009-11-10

申请号：US11764980

申请日：2007-06-19

申请人： Amitabh Jain ,  Manoj Mehrotra

发明人： Amitabh Jain ,  Manoj Mehrotra

IPC分类号： H01L21/331

CPC分类号： H01L21/2652 ,  H01L21/2255 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/823814 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底上形成栅极电介质层。 在栅极电介质层上形成栅电极。 将掺杂剂注入到衬底的延伸区域中，其中掺杂剂的量保留在与栅电极相邻的电介质层中。 衬底在约1000℃或更高的温度下进行退火，以使掺杂剂的量的至少一部分扩散到半导体衬底中。

公开(公告)号：US20090065880A1

公开(公告)日：2009-03-12

申请号：US11853328

申请日：2007-09-11

申请人： Amitabh Jain ,  Manoj Mehrotra

发明人： Amitabh Jain ,  Manoj Mehrotra

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28044 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845

摘要： In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal.

摘要翻译： 在一个方面，提供一种制造半导体器件的方法，包括在半导体衬底上形成栅电极，在栅电极附近形成源极/漏极，在栅电极上沉积应力诱导层。 在至少约1100℃的温度下沉积应力诱导层至少约300微秒的时间之后，至少在栅电极上进行激光退火，并且半导体器件经受热 在进行激光退火之后退火。

公开(公告)号：US20080308904A1

公开(公告)日：2008-12-18

申请号：US11763497

申请日：2007-06-15

申请人： P. R. Chidambaram ,  Srinivasan Chakravarthi ,  Mahalingam Nandakumar ,  Manoj Mehrotra ,  Amitabh Jain ,  Thomas D. Bonifield

发明人： P. R. Chidambaram ,  Srinivasan Chakravarthi ,  Mahalingam Nandakumar ,  Manoj Mehrotra ,  Amitabh Jain ,  Thomas D. Bonifield

IPC分类号： H01L21/425 ,  H01L29/36

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66068 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A method of manufacturing a semiconductor device. The method comprises providing C atoms in a semiconductor substrate. The method also comprises implanting In atoms and p-type dopants into a predefined region of the substrate that is configured to have the carbon atoms. The method further comprises thermally annealing the semiconductor substrate to transform the predefined region into an activated doped region.

摘要翻译： 一种制造半导体器件的方法。 该方法包括在半导体衬底中提供C原子。 该方法还包括将In原子和p型掺杂剂注入被配置为具有碳原子的衬底的预定区域中。 该方法还包括对半导体衬底进行热退火以将预定区域转变为激活的掺杂区域。

公开(公告)号：US20080318387A1

公开(公告)日：2008-12-25

申请号：US11764980

申请日：2007-06-19

申请人： Amitabh Jain ,  Manoj Mehrotra

发明人： Amitabh Jain ,  Manoj Mehrotra

IPC分类号： H01L21/336

CPC分类号： H01L21/2652 ,  H01L21/2255 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/823814 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底上形成栅极电介质层。 在栅极电介质层上形成栅电极。 将掺杂剂注入到衬底的延伸区域中，其中掺杂剂的量保留在与栅电极相邻的电介质层中。 衬底在约1000℃或更高的温度下进行退火，以使掺杂剂的量的至少一部分扩散到半导体衬底中。

公开(公告)号：US20080268628A1

公开(公告)日：2008-10-30

申请号：US11739965

申请日：2007-04-25

申请人： Puneet Kohli ,  Manoj Mehrotra ,  Antonio Luis Pacheco Rotondaro ,  Stan Ashburn ,  Nandakumar Mahalingam ,  Amitabh Jain

发明人： Puneet Kohli ,  Manoj Mehrotra ,  Antonio Luis Pacheco Rotondaro ,  Stan Ashburn ,  Nandakumar Mahalingam ,  Amitabh Jain

IPC分类号： H01L21/425 ,  H01L29/00 ,  H01L21/22

CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L29/66575

摘要： The disclosure relates to a method of forming an n-type doped active area on a semiconductor substrate that presents an improved placement profile. The method comprises the placement of arsenic in the presence of a carbon-containing arsenic diffusion suppressant in order to reduce the diffusion of the arsenic out of the target area during heat-induced annealing. The method may additionally include the placement of an amorphizer, such as germanium, in the target area in order to reduce channeling of the arsenic ions through the crystalline lattice. The method may also include the use of arsenic in addition to another n-type dopant, e.g. phosphorus, in order to offset some of the disadvantages of a pure arsenic dopant. The disclosure also relates to a semiconductor component, e.g. an NMOS transistor, formed in accordance with the described methods.

摘要翻译： 本公开涉及一种在半导体衬底上形成n型掺杂有源区的方法，该方法具有改善的放置曲线。 该方法包括在含碳的砷扩散抑制剂的存在下放置砷，以便在热诱导退火期间减少砷扩散到目标区域之外。 该方法可以另外包括在目标区域中放置诸如锗的非晶硅化合物，以便减少砷离子通过晶格的通道。 该方法还可以包括除了另一种n型掺杂剂之外使用砷，例如， 磷，以便抵消纯砷掺杂剂的一些缺点。 本公开还涉及半导体部件，例如， 一个根据所述方法形成的NMOS晶体管。

公开(公告)号：US07344929B2

公开(公告)日：2008-03-18

申请号：US11034791

申请日：2005-01-13

申请人： Manoj Mehrotra ,  Amitabh Jain

发明人： Manoj Mehrotra ,  Amitabh Jain

IPC分类号： H01L21/00

CPC分类号： H01L21/324 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer (210) over a transistor device having source/drain regions (150, 155) located over a substrate (110), the capping layer (210) having a degree of reflectivity, and annealing the transistor device through the capping layer (210) using photons (310), the annealing of the transistor device affected by the degree of reflectivity.

摘要翻译： 本发明提供一种制造半导体器件的方法和集成电路的制造方法。 除了其他步骤之外，制造半导体器件的方法包括在具有位于衬底（110）上方的源/漏区（150,155）的晶体管器件上形成覆盖层（210），所述覆盖层（210）具有 并且通过使用光子（310）的覆盖层（210）退火晶体管器件，晶体管器件的退火受到反射率的影响。

公开(公告)号：US20060154475A1

公开(公告)日：2006-07-13

申请号：US11034791

申请日：2005-01-13

申请人： Manoj Mehrotra ,  Amitabh Jain

发明人： Manoj Mehrotra ,  Amitabh Jain

IPC分类号： H01L21/4763 ,  H01L21/324

CPC分类号： H01L21/324 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/7833

摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a capping layer (210) over a transistor device having source/drain regions (150, 155) located over a substrate (110), the capping layer (210) having a degree of reflectivity, and annealing the transistor device through the capping layer (210) using photons (310), the annealing of the transistor device affected by the degree of reflectivity.

摘要翻译： 本发明提供一种制造半导体器件的方法和集成电路的制造方法。 除了其他步骤之外，制造半导体器件的方法包括在具有位于衬底（110）上方的源/漏区（150,155）的晶体管器件上形成覆盖层（210），所述覆盖层（210）具有 并且通过使用光子（310）的覆盖层（210）退火晶体管器件，晶体管器件的退火受到反射率的影响。

公开(公告)号：US06743705B2

公开(公告)日：2004-06-01

申请号：US10287979

申请日：2002-11-05

申请人： Manoj Mehrotra ,  Haowen Bu ,  Amitabh Jain

发明人： Manoj Mehrotra ,  Haowen Bu ,  Amitabh Jain

IPC分类号： H01L214763

CPC分类号： H01L29/6659 ,  H01L29/6656

摘要： A method (40) of forming an integrated circuit (60) device including a substrate (64). The method including the step of first (42), forming a gate stack (62) in a fixed relationship to the substrate, the gate stack including a gate having sidewalls. The method further includes the step of second (42), implanting source/drain extensions (701, 702) into the substrate and self-aligned relative to the gate stack. The method further includes the steps of third (46, 48), forming a first sidewall-forming layer (72) in a fixed relationship to the sidewalls and forming a second sidewall-forming layer (74) in a fixed relationship to the sidewalls. The step of forming a second sidewall-forming layer includes depositing the second sidewall-forming layer at a temperature equal to or greater than approximately 850° C. The method further includes the step of fourth (50), implanting deep source/drain regions (761, 762) into the substrate and self-aligned relative to the gate stack and the first and second sidewall-forming layers.

摘要翻译： 一种形成包括衬底（64）的集成电路（60）装置的方法（40）。 该方法包括第一步骤（42）的步骤，与衬底形成固定关系的栅叠层（62），栅叠层包括具有侧壁的栅极。 该方法还包括第二步骤（42），将源极/漏极延伸部分（701,702）注入到衬底中并相对于栅极堆叠自对准。 该方法还包括第三（46,48）的步骤，形成与侧壁成固定关系的第一侧壁形成层（72），并形成与侧壁成固定关系的第二侧壁形成层（74）。 形成第二侧壁形成层的步骤包括在等于或大于约850℃的温度下沉积第二侧壁形成层。该方法还包括第四（50）的步骤，将深源/漏区（ 761,762）插入衬底并且相对于栅极堆叠以及第一和第二侧壁形成层自对准。