-
71.发明授权Digital to analog converter using level and timing control signals to cancel noise 失效数模转换器采用电平和定时控制信号消除噪声公开(公告)号：US06373417B1
公开(公告)日：2002-04-16
申请号：US09510818
申请日：2000-02-23
IPC分类号： H03M300
CPC分类号： H03M3/506 , H03M7/3022
摘要： A multiple stage delta sigma converter includes a first delta sigma modulator providing a first modulator output signal, a second delta sigma modulator providing a second output signal, and a pulse wave modulator for generating formatted output wherein the level (width) of the formatted output is dependent upon the first modulator output and the timing (delay) of the formatted output is dependent upon the second modulator output. The second modulator output is also based upon the first modulator feedback signal. The second modulator quantizer output and feedback signal are constrained by an output of the first converter. A 1 bit digital to analog converter connected to the output of the PWM converts the formatted output signal to an analog signal.
摘要翻译： 多级Δ-Σ转换器包括提供第一调制器输出信号的第一ΔΣ调制器，提供第二输出信号的第二ΔΣ调制器和用于产生格式化输出的脉冲波调制器，其中格式化输出的电平（宽度） 取决于第一调制器输出和格式化输出的定时（延迟）取决于第二调制器输出。 第二调制器输出也基于第一调制器反馈信号。 第二调制器量化器输出和反馈信号由第一转换器的输出约束。 连接到PWM输出的1位数模转换器将格式化的输出信号转换为模拟信号。
-
公开(公告)号：US5896101A
公开(公告)日：1999-04-20
申请号：US710371
申请日：1996-09-16
摘要： In a delta sigma modulator, generally comprising one or more integrators fed into a multilevel quantizer, the output of which is the output of the delta sigma modulator and is also fed through a digital to analog converter in a feedback loop to the integrators, the quantizer is made sparse, i.e. the levels output by the quantizer are not evenly spaced, but rather are closely spaced for small deviations from 0 V, and broadly spaced for large deviations from 0V. The A/D converter in the feedback is matched to the quantizer. For example, the levels might be -1 V, -1/8 V, 0V, 1/8 V, and 1 V. The digital output signal from the sparse quantizer is fed into a correction RAM, which corrects for nonlinearities in the D/A converter before the digital signal is filtered by a low pass filter and frequency down converted. The contents of the RAM are selected whenever the A/D conversion system is powered on. The contents of the RAM are selected by closing a series of sets switches in the A/D converter and adjusting the output of the RAM to 0.
摘要翻译： 在ΔΣ调制器中，通常包括馈送到多电平量化器中的一个或多个积分器，其输出是ΔΣ调制器的输出，并且还通过反馈回路中的数模转换器馈送到积分器，量化器 是稀疏的，即由量化器输出的电平不是均匀间隔的，而是与0V的小偏差紧密隔开，并且与0V的大偏差大致间隔开。 反馈中的A / D转换器与量化器匹配。 例如，电平可能是-1V，-1 / 8V，0V，1/8V和1V。来自稀疏量化器的数字输出信号被馈送到校正RAM中，其校正D中的非线性 / A转换器之前，数字信号被低通滤波器滤波并降频转换。 只要A / D转换系统上电，RAM内容就会被选中。 通过关闭A / D转换器中的一系列开关并将RAM的输出调整为0来选择RAM的内容。
-
公开(公告)号：US20100156319A1
公开(公告)日：2010-06-24
申请号：US12339651
申请日：2008-12-19
IPC分类号： H05B37/02
CPC分类号： H05B33/0815 , H05B33/0818 , H05B33/0848 , H05B33/086 , Y02B20/347
摘要： A light emitting diode (LED) lighting system and method are disclosed. The LED lighting system and method include an LED controller to accurately control a current in an LED system. The LED controller includes components to calculate, based on the current and an active time period of an LED current time period, an actual charge amount delivered to the LED system wherein the LED current time period is duty cycle, modulated at a rate of greater than fifty (50) Hz and to utilize the actual charge amount to modify and provide a desired target charge amount to be delivered during a future active time period of the LED current time period. The LED system and method further involve components to compare the actual charge amount to a desired charge amount for the active time period and compensate for a difference between the actual charge amount and the desired charge amount during the future active time period.
摘要翻译： 公开了一种发光二极管（LED）照明系统和方法。 LED照明系统和方法包括用于精确地控制LED系统中的电流的LED控制器。 LED控制器包括基于LED当前时间段的电流和有效时间段来计算传送到LED系统的实际充电量的组件，其中LED当前时间周期是占空比，以大于 并且利用实际电荷量修改并提供在LED当前时间段的未来有效时间段期间要传送的期望目标电荷量。 LED系统和方法还包括将实际电荷量与活动时间段期望的电荷量进行比较的部件，并补偿在未来的有效时间段期间实际电荷量与期望充电量之间的差值。
-
74.发明授权Luminance/chrominance video data separation circuits and methods and video systems utilizing the same 有权亮度/色度视频数据分离电路和利用其的方法和视频系统公开(公告)号：US07538823B1
公开(公告)日：2009-05-26
申请号：US11234788
申请日：2005-09-23
IPC分类号： H04N9/78
CPC分类号： H04N9/78
摘要： A method of separating a chroma data component from a video data stream includes determining a phase relationship between a color burst in digital video data samples of a composite video signal and a local clock signal which processes the digital video data samples. In response to determining the phase relationship, interpolation filtering is performed on the digital video data samples corresponding to first and second display lines to generate phase aligned video data samples. Adaptive filtering is then performed utilizing the phase aligned video data samples corresponding to the first and second display lines to separate the chroma component from the digital video data samples corresponding to the first display line.
摘要翻译： 从视频数据流中分离色度数据分量的方法包括确定复合视频信号的数字视频数据样本中的色同步信号与处理数字视频数据样本的本地时钟信号之间的相位关系。 响应于确定相位关系，对与第一和第二显示行相对应的数字视频数据样本执行内插滤波，以产生相位对准的视频数据采样。 然后利用对应于第一和第二显示行的相位对准的视频数据采样来执行自适应滤波，以将色度分量与对应于第一显示行的数字视频数据样本分离。
-
公开(公告)号：US07391842B1
公开(公告)日：2008-06-24
申请号：US11432113
申请日：2006-05-11
IPC分类号： H03D3/24
CPC分类号： H03L7/185 , G06F1/0321 , G06F1/0353 , H03L2207/12
摘要： Clock signal generation circuitry includes input circuitry for receiving a frequency control input signal and a clock signal and generating a memory address therefrom, a memory for storing digital data indexed by the memory address and representing real and imaginary parts of a complex digital waveform, and digital to analog conversion circuitry. The digital to analog conversion circuitry includes real-part digital to analog conversion circuitry for converting digital data retrieved from the memory and representing the real part of the complex waveform into a real-part analog signal and imaginary-part digital to analog conversion circuitry for converting digital data retrieved from the memory and representing the imaginary part of the complex waveform into an imaginary-part analog signal. The clock signal generation circuitry also includes analog filtering circuitry having real-part filtering circuitry for filtering the real-part analog signal to generate a filtered real-part analog signal and imaginary-part filtering circuitry for filtering the imaginary-part analog signal to generate a filtered imaginary-part analog signal. Analog to digital conversion circuitry is provided for converting the filtered real-part and imaginary-part analog signals into a digital clock signal at a rate near an integer multiple of a frequency of the filtered real-part and imaginary-part analog signals.
摘要翻译： 时钟信号产生电路包括用于接收频率控制输入信号和时钟信号并从其产生存储器地址的输入电路，用于存储由存储器地址索引并表示复数数字波形的实部和虚部的数字数据的存储器，以及数字 到模拟转换电路。 数模转换电路包括实部数字到模拟转换电路，用于转换从存储器检索的数字数据，并将复数波形的实部表示为实部模拟信号和虚部数模转换电路，用于转换 从存储器检索的数字数据，并将复数波形的虚部表示成虚部模拟信号。 时钟信号产生电路还包括具有实部滤波电路的模拟滤波电路，用于对实部模拟信号进行滤波以产生经滤波的实部模拟信号和虚部滤波电路，用于对虚部模拟信号进行滤波以产生 滤波的虚部模拟信号。 提供模数转换电路，用于将滤波的实部和虚部模拟信号以接近滤波后的实部和虚部模拟信号的频率的整数倍的速率转换为数字时钟信号。
-
76.发明授权公开(公告)号：US07199744B1
公开(公告)日：2007-04-03
申请号：US11258668
申请日：2005-10-26
IPC分类号： H03M1/82
CPC分类号： H03F1/26 , H03F3/2173 , H03F2200/294 , H03F2200/331 , H03F2200/351 , H03F2200/372 , H04B15/04 , H04B2215/065 , H04B2215/069
摘要： A method of generating a pulse width modulated data stream includes providing a first clock signal having a first frequency and selecting a divisor from a set of divisors for dividing the first frequency to select a pattern rate of a pulse width modulated data stream and thereby shift in frequency noise generated at the pattern rate during pulse width modulation. The first frequency of the first signal is divided to generate a second signal at the selected pattern rate. Noise shaping and requantizing is performed on the second signal to generate a noise shaped and requantized second signal and the pulse width modulated data stream having patterns at the selected pattern rate is generated in response to the first signal and the noise shaped and requantized second signal.
摘要翻译： 一种产生脉宽调制数据流的方法包括：提供具有第一频率的第一时钟信号，并从一组除数中选择除数，以分频第一频率以选择脉宽调制数据流的模式速率， 在脉冲宽度调制期间以图案速率产生的频率噪声。 第一信号的第一频率被分割以产生所选择的模式速率的第二信号。 对第二信号执行噪声整形和再量化以产生噪声形状和再量化的第二信号，并且响应于第一信号和噪声形状和再量化的第二信号产生具有所选模式速率的模式的脉宽调制数据流。
-
77.发明授权Digital data processing circuits and systems with delta-sigma modulator filtering 失效具有Δ-Σ调制器滤波的数字数据处理电路和系统公开(公告)号：US07194036B1
公开(公告)日：2007-03-20
申请号：US10397540
申请日：2003-03-26
CPC分类号： H03M7/304 , H03M7/3026 , H03M7/3028
摘要： A method of processing a digital data stream in a digital processing system includes filtering the digital data stream being processed through a delta-sigma modulator having a selected signal transfer function passing a frequency band of interest.
摘要翻译： 一种在数字处理系统中处理数字数据流的方法包括：通过具有通过感兴趣频带的选定信号传递函数的Δ-Σ调制器对正在处理的数字数据流进行滤波。
-
78.发明授权Circuits, systems and methods for volume control in low noise 1-bit digital audio systems 有权低噪声1位数字音频系统中音量控制的电路，系统和方法公开(公告)号：US07173550B1
公开(公告)日：2007-02-06
申请号：US10912627
申请日：2004-08-05
IPC分类号： H03M3/00
CPC分类号： H03M7/304 , G11B20/10527 , H03G3/002 , H03M7/3026
摘要： A method of amplitude control in a 1-bit digital system includes the step of scaling the stream of 1-bit data by a scaling factor corresponding to a selected output amplitude. The scaled data is modulated and the resulting modulated, scaled data is converted from digital to analog form.
摘要翻译： 1位数字系统中的幅度控制方法包括按照与所选择的输出振幅对应的比例因子来缩放1比特数据流的步骤。 经缩放的数据被调制，并且所得到的调制的，缩放的数据从数字模式转换成模拟形式。
-
79.发明授权Gain or input volume controller and method utilizing a modified R2R ladder network 失效增益或输入音量控制器和使用修改的R2R梯形网络的方法公开(公告)号：US07162029B2
公开(公告)日：2007-01-09
申请号：US10447606
申请日：2003-05-29
摘要： A gain or input volume controller and method includes a modified R2R ladder network having a number of R2R branches, switches coupled respectively to the R2R branches, and a switch controller for respectively controlling the switches to control and provide an overall gain value for a signal. The switch controller further includes a mapper for mapping a gain control signal to the switches wherein the gain control signal respectively activates or deactivates the switches. A fine gain control stage provides a fine gain control of the overall gain value. A coarse gain control stage is coupled to the fine gain control stage. The coarse gain control stage includes the modified R2R ladder network and provides a coarse gain control of the overall gain value.
摘要翻译： 增益或输入音量控制器和方法包括具有多个R2R分支，分别耦合到R2R分支的开关的修改的R2R梯形网络和用于分别控制开关以控制并提供信号的总增益值的开关控制器。 开关控制器还包括用于将增益控制信号映射到开关的映射器，其中增益控制信号分别激活或去激活开关。 精细增益控制级提供整体增益值的精细增益控制。 粗调增益控制级耦合到微增益控制级。 粗增益控制级包括经修改的R2R梯形网络，并提供总增益值的粗增益控制。
-
公开(公告)号：US07116721B1
公开(公告)日：2006-10-03
申请号：US10151322
申请日：2002-05-20
申请人： John Laurence Melanson , Heling Yi
发明人： John Laurence Melanson , Heling Yi
CPC分类号： H03M7/304 , H03M7/3026 , H03M7/3028
摘要： A feedback noise-shaper of an order of at least three implements a first pole set defining a signal transfer function of a selected corner frequency and a second pole set having at least one pole at a frequency at least twice the selected corner frequency defining a noise transfer function.
摘要翻译： 至少三个级别的反馈噪声整形器实现了定义所选转角频率的信号传递函数的第一极点集合和具有至少一个极点的第二极点，频率至少为所选转角频率的两倍，所述转角频率限定噪声 传递函数。
-
-
-
-
-
-
-
-
-
搜索结果
92 条记录 (耗时 0.17 秒)
