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    REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES
    74.
    发明申请
    REDUCING EXTERNAL RESISTANCE OF A MULTI-GATE DEVICE USING SPACER PROCESSING TECHNIQUES 审中-公开
    使用间隔加工技术降低多门装置的外部电阻

    公开(公告)号：US20110284965A1

    公开(公告)日：2011-11-24

    申请号：US13204987

    申请日：2011-08-08

    申请人： Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

    发明人： Ravi Pillarisetty ,  Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66795 ,  H01L29/66545 ,  H01L29/785

    摘要： Reducing external resistance of a multi-gate device using spacer processing techniques is generally described. In one example, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins, the one or more multi-gate fins comprising a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins, forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins, removing the sacrificial gate electrode from the gate region of the one or more to multi-gate fins, depositing spacer gate dielectric to the gate region of the one or more multi-gate fins wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film, and etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.

    摘要翻译： 通常描述使用间隔物处理技术降低多栅极器件的外部电阻。 在一个示例中，一种方法包括将牺牲栅电极沉积到一个或多个多栅极散热片上，一个或多个多栅极鳍片包括栅极区域，源极区域和漏极区域，栅极区域设置在 源极和漏极区域，图案化牺牲栅极电极，使得牺牲栅电极材料耦合到栅极区域，并且基本上没有牺牲栅极电极耦合到一个或多个多栅极鳍片的源极和漏极区域，形成电介质 将一个或多个多栅极翅片的源极和漏极区域耦合到所述一个或多个多栅极散热片的栅极区域;将所述牺牲栅极电极从所述一个或多个至多个栅极鳍片的栅极区域移除;将间隔栅极电介质沉积到所述一个或多个栅极栅极栅极区域; 更多的多栅极鳍片，其中基本上没有间隔栅极电介质沉积到一个或多个多栅极鳍片的源极和漏极区域，源极和漏极区域被电介质保护 膜和蚀刻间隔栅极电介质以从栅极区域区域完全去除间隔栅极电介质，以与最终栅极电极耦合，除了与保持耦合的最终栅电极耦合的间隔栅极电介质的剩余预定厚度之外 与电介质膜。

    Dual crystal orientation circuit devices on the same substrate
    80.
    发明申请
    Dual crystal orientation circuit devices on the same substrate 有权
    双晶体取向电路器件在同一基片上

    公开(公告)号：US20080079003A1

    公开(公告)日：2008-04-03

    申请号：US11529974

    申请日：2006-09-29

    申请人： Mohamad A. Shaheen ,  Peter Tolchinsky ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Suman Datta ,  David Simon

    发明人： Mohamad A. Shaheen ,  Peter Tolchinsky ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Suman Datta ,  David Simon

    IPC分类号： H01L29/04 ,  H01L21/00

    CPC分类号： H01L29/045 ,  H01L29/66795 ,  H01L29/7851

    摘要： Embodiments of the invention provide a substrate with a device layer having different crystal orientations in different portions or areas. One layer of material having one crystal orientation may be bonded to a substrate having another crystal orientation. Then, a portion of the layer may be amorphized and annealed to be re-crystallized to the crystal orientation of the substrate. N- and P-type devices, such as tri-gate devices, may both be formed on the substrate, with each type of device having the proper crystal orientation along the top and side surfaces of the claimed region for optimum performance. For instance, a substrate may have a portion with a crystal orientation along a top and sidewalls of an NMOS tri-gate transistor and another portion having a crystal orientation along parallel top and sidewall surfaces of a PMOS tri-gate transistor.

    摘要翻译： 本发明的实施例提供了具有在不同部分或区域中具有不同晶体取向的器件层的衬底。 具有一个晶体取向的一层材料可以结合到具有另一晶体取向的衬底。 然后，该层的一部分可以非晶化并退火，以再结晶到衬底的晶体取向。 可以在衬底上形成N型和P型器件，例如三栅极器件，每种类型的器件沿着所要求保护的区域的顶表面和侧表面具有适当的晶体取向，以获得最佳性能。 例如，衬底可以具有沿着NMOS三栅极晶体管的顶部和侧壁具有<100>晶体取向的部分，并且沿着PMOS三栅极的平行顶部和侧壁表面具有<110>晶体取向的另一部分 晶体管。