公开(公告)号：US07670928B2

公开(公告)日：2010-03-02

申请号：US11453444

申请日：2006-06-14

申请人： Mohamad A. Shaheen ,  Willy Rachmady ,  Peter Tolchinsky

发明人： Mohamad A. Shaheen ,  Willy Rachmady ,  Peter Tolchinsky

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76251 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01021 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A multi-layered substrate with bulk substrate characteristics and processes for the fabrication of such substrates are herein disclosed. The multi-layered substrate can include a first layer, a second layer and an interfacial layer therebetween. The first and second layers can be silicon, germanium, or any other suitable material of the same or different crystal orientations. The interfacial layer can be an oxide layer from about 5 Angstroms to about 50 Angstroms.

摘要翻译： 本文公开了具有体基板特性的多层基板和用于制造这种基板的工艺。 多层基板可以包括第一层，第二层和它们之间的界面层。 第一层和第二层可以是硅，锗或具有相同或不同晶体取向的任何其它合适的材料。 界面层可以是约5埃至约50埃的氧化物层。

公开(公告)号：US20060102988A1

公开(公告)日：2006-05-18

申请号：US10987775

申请日：2004-11-12

申请人： Peter Tolchinsky ,  Martin Giles ,  Michael McSwiney ,  Mohamad Shaheen ,  Irwin Yablok

发明人： Peter Tolchinsky ,  Martin Giles ,  Michael McSwiney ,  Mohamad Shaheen ,  Irwin Yablok

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/26533 ,  H01L21/76243

摘要： Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.

摘要翻译： 公开了具有覆盖掩埋氧化物层的蚀刻停止层的绝缘体上硅（SOI）晶片的实施例以及其制造方法的实施例。 蚀刻停止层可以包括氮化硅，氮掺杂二氧化硅或氮氧化硅，以及这些材料的某些组合。 描述和要求保护其他实施例。

公开(公告)号：US20050217560A1

公开(公告)日：2005-10-06

申请号：US10815427

申请日：2004-03-31

申请人： Peter Tolchinsky ,  Mohamad Shaheen ,  Irwin Yablok

发明人： Peter Tolchinsky ,  Mohamad Shaheen ,  Irwin Yablok

IPC分类号： C30B1/00 ,  C30B15/36 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14 ,  H01L21/762

CPC分类号： H01L21/76256 ,  C30B15/36 ,  H01L21/76254

摘要： The crystal orientations of monocrystalline semiconductor wafers may be varied by four parameters. The first parameter is the type of crystal seed used to grow the monocrystalline semiconductor ingot from which the wafers are cut. The second parameter is the angle at which the wafer is sliced from the ingot. The third parameter is the crystal plane towards which the wafer is cut. And, the fourth parameter is the position of the orientation indication feature that is used to align the wafer during processing. Different combinations of these parameters provide variations of non-standard crystal orientations of monocrystalline semiconductor wafers and semiconductor-on-insulator substrates such as silicon-on-insulator.

摘要翻译： 单晶半导体晶片的晶体取向可以通过四个参数来改变。 第一个参数是用于生长切割晶片的单晶半导体晶锭的晶种种类。 第二个参数是从晶锭切片晶片的角度。 第三参数是切割晶片的晶体平面。 而且，第四参数是在处理期间用于对准晶片的取向指示特征的位置。 这些参数的不同组合提供单晶半导体晶片和绝缘体上半导体衬底（例如绝缘体上硅）的非标准晶体取向的变化。

公开(公告)号：US20070063279A1

公开(公告)日：2007-03-22

申请号：US11231002

申请日：2005-09-16

申请人： Peter Tolchinsky ,  Mohamad Shaheen ,  Martin Giles ,  Irwin Yablok ,  Aaron Budrevich

发明人： Peter Tolchinsky ,  Mohamad Shaheen ,  Martin Giles ,  Irwin Yablok ,  Aaron Budrevich

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392 ,  H01L21/84 ,  H01L21/00

CPC分类号： H01L21/76243

摘要： A method of forming a silicon-on-insulator wafer begins by providing a silicon wafer having a first surface. An ion implantation process is then used to implant oxygen within the silicon wafer to form an oxygen layer that is buried within the silicon wafer, thereby forming a silicon device layer that remains substantially free of oxygen between the oxygen layer and the first surface. An annealing process is then used to diffuse nitrogen into the silicon wafer, wherein the nitrogen diffuses into the silicon device layer and the oxygen layer. Finally, a second annealing process is used to form a silicon dioxide layer and a silicon oxynitride layer, wherein the second annealing process causes the implanted oxygen to react with the silicon to form the silicon dioxide layer and causes the diffused nitrogen to migrate and react with the silicon and the implanted oxygen to form the silicon oxynitride layer.

摘要翻译： 形成绝缘体上硅晶片的方法开始于提供具有第一表面的硅晶片。 然后使用离子注入工艺将氧气注入到硅晶片内以形成掩埋在硅晶片内的氧层，由此形成在氧层和第一表面之间基本上不含氧的硅器件层。 然后使用退火工艺将氮扩散到硅晶片中，其中氮扩散到硅器件层和氧层中。 最后，使用第二退火工艺形成二氧化硅层和氧氮化硅层，其中第二退火工艺使注入的氧与硅反应形成二氧化硅层，并使扩散的氮迁移并与 硅和注入的氧以形成氮氧化硅层。

公开(公告)号：US07161224B2

公开(公告)日：2007-01-09

申请号：US11103217

申请日：2005-04-11

申请人： Peter Tolchinsky ,  Mohamad Shaheen ,  Ryan Lei ,  Irwin Yablok

发明人： Peter Tolchinsky ,  Mohamad Shaheen ,  Ryan Lei ,  Irwin Yablok

IPC分类号： H01L29/00

CPC分类号： H01L21/67092 ,  B23K20/023 ,  B23K2101/40 ,  H01L21/187 ,  H01L21/76251

摘要： More complete bonding of wafers may be achieved out to the edge regions of the wafer by constrained bond strengthening of the wafers in a pressure bonding apparatus after direct wafer bonding. The pressure bonding process may be accompanied by the application of not above room temperature.

摘要翻译： 可以通过在直接晶片接合之后的压接装置中的晶片的约束粘结强化来实现晶片的更完全的接合到晶片的边缘区域。 压接过程可能伴随不高于室温的应用。

公开(公告)号：US07091108B2

公开(公告)日：2006-08-15

申请号：US10661738

申请日：2003-09-11

申请人： Peter Tolchinsky ,  Irwin Yablok ,  Chuan Hu ,  Richard D. Emery

发明人： Peter Tolchinsky ,  Irwin Yablok ,  Chuan Hu ,  Richard D. Emery

IPC分类号： H01L21/46

CPC分类号： H01L21/6835 ,  H01L21/3063 ,  H01L21/76254 ,  H01L23/367 ,  H01L24/81 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/181 ,  Y10S438/96 ,  H01L2924/00012 ,  H01L2924/00

摘要： Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.

公开(公告)号：US20150203651A1

公开(公告)日：2015-07-23

申请号：US14159145

申请日：2014-01-20

申请人： Gregory Peter Tolchinsky

发明人： Gregory Peter Tolchinsky

IPC分类号： C08K3/04

CPC分类号： C08K3/04 ,  C08K2201/011

摘要： The invention discloses a shoe sole material with a high wear resistance and the method of manufacturing the sole material. The disclosed shoe sole composition includes nano-diamond produced by the shock wave method as an inorganic reinforcing filler. The inclusion of nano-diamond as a reinforcing filler increases the life of the shoe sole while reducing the total weight of the shoe. Other reinforcing inorganic fillers such as black carbon, silicon carbide, alumina, etc., can be used in the shoe sole rubber composition in addition to nano-diamond.

摘要翻译： 本发明公开了具有高耐磨性的鞋底材料和制造鞋底材料的方法。 所公开的鞋底组合物包括通过冲击波法制造的纳米金刚石作为无机增强填料。 包含纳米金刚石作为增强填料增加了鞋底的寿命，同时减少了鞋的总重量。 除了纳米金刚石之外，其它增强无机填料如黑碳，碳化硅，氧化铝等可用于鞋底橡胶组合物中。

公开(公告)号：US07569857B2

公开(公告)日：2009-08-04

申请号：US11529974

申请日：2006-09-29

申请人： David Simon, legal representative ,  Peter Tolchinsky ,  Jack T Kavalieros ,  Brian S Doyle ,  Suman Datta

发明人： Mohamad A. Shaheen

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L29/66795 ,  H01L29/7851

摘要： Embodiments of the invention provide a substrate with a device layer having different crystal orientations in different portions or areas. One layer of material having one crystal orientation may be bonded to a substrate having another crystal orientation. Then, a portion of the layer may be amorphized and annealed to be re-crystallized to the crystal orientation of the substrate. N- and P-type devices, such as tri-gate devices, may both be formed on the substrate, with each type of device having the proper crystal orientation along the top and side surfaces of the claimed region for optimum performance. For instance, a substrate may have a portion with a crystal orientation along a top and sidewalls of an NMOS tri-gate transistor and another portion having a crystal orientation along parallel top and sidewall surfaces of a PMOS tri-gate transistor.

摘要翻译： 本发明的实施例提供了具有在不同部分或区域中具有不同晶体取向的器件层的衬底。 具有一个晶体取向的一层材料可以结合到具有另一晶体取向的衬底。 然后，该层的一部分可以非晶化并退火，以再结晶到衬底的晶体取向。 可以在衬底上形成N型和P型器件，例如三栅极器件，每种类型的器件沿着所要求保护的区域的顶表面和侧表面具有适当的晶体取向，以获得最佳性能。 例如，衬底可以具有沿着NMOS三栅极晶体管的顶部和侧壁具有<100>晶体取向的部分，并且沿着PMOS三栅极的平行顶部和侧壁表面具有<110>晶体取向的另一部分 晶体管。

公开(公告)号：US07531429B2

公开(公告)日：2009-05-12

申请号：US11397412

申请日：2006-04-03

申请人： Peter Tolchinsky ,  Irwin Yablok ,  Chuan Hu ,  Richard D. Emery

发明人： Peter Tolchinsky ,  Irwin Yablok ,  Chuan Hu ,  Richard D. Emery

IPC分类号： H01L21/46 ,  H01L21/30 ,  H01L21/76 ,  H01L21/00 ,  H01L21/762

CPC分类号： H01L21/6835 ,  H01L21/3063 ,  H01L21/76254 ,  H01L23/367 ,  H01L24/81 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/181 ,  Y10S438/96 ,  H01L2924/00012 ,  H01L2924/00

摘要： Embodiments of the invention use silicon on porous silicon wafers to produce a reduced-thickness IC device wafers. After device manufacturing, a temporary support is bonded to the device layer. The uppermost silicon layer is then separated from the silicon substrate by splitting the porous silicon layer. The porous silicon layer and temporary support are then removed and packaging is completed. Embodiments of the invention provide reliable, low cost methods and apparatuses for producing reduced-thickness IC device wafers to substantially increase thermal conductivity between the device layer of an IC device and a heat sink. In alternative embodiments, the layered silicon substrate includes an insulator layer on a layer of porous silicon and a silicon layer on the insulator layer.

摘要翻译： 本发明的实施例在多孔硅晶片上使用硅来制造厚度较薄的IC器件晶片。 在器件制造之后，临时支撑件被结合到器件层。 然后通过分离多孔硅层将最上层的硅层与硅衬底分离。 然后去除多孔硅层和临时支撑物，并且完成包装。 本发明的实施例提供了可靠的，低成本的方法和装置，用于生产较薄的IC器件晶片，以显着增加IC器件的器件层与散热片之间的热导率。 在替代实施例中，分层硅衬底包括在多孔硅层上的绝缘体层和绝缘体层上的硅层。

公开(公告)号：US20060138627A1

公开(公告)日：2006-06-29

申请号：US11025131

申请日：2004-12-29

申请人： Mohamad Shaheen ,  Peter Tolchinsky ,  Irwin Yablok ,  Scott List

发明人： Mohamad Shaheen ,  Peter Tolchinsky ,  Irwin Yablok ,  Scott List

IPC分类号： H01L21/30 ,  H01L23/02

CPC分类号： H01L24/81 ,  H01L21/6835 ,  H01L21/76259 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2924/01033 ,  H01L2924/14

摘要： A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.

摘要翻译： 一种提供三维（3-D）IC晶片工艺流程的方法和制品。 在一些实施例中，所述方法和制品包括将多层晶片的器件层接合到另一多层晶片的器件层以形成键合的器件层对，所述多层晶片中的每一个在多孔硅层上包括硅层 （SiOPSi），其中所述器件层形成在所述硅层中，通过分离所述多孔硅层之一将所述一对器件层与所述硅衬底中的一个分离，并且将所述一对器件层与所述多个硅层分离 通过分离另一个多孔硅层来提供剩余的硅衬底以提供垂直堆叠的晶片。