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公开(公告)号：US06632343B1
公开(公告)日：2003-10-14
申请号：US09651040
申请日：2000-08-30
IPC分类号： C25D502
CPC分类号： H05K3/242 , H05K1/0346 , H05K1/0373 , H05K3/243 , H05K2201/0154 , H05K2201/0323 , H05K2203/1142
摘要： A method and apparatus for electrolytic plating of selected areas of printed circuit board traces is disclosed. The method is characterized by its elimination of the need for plating bus bars and plating contacts on the printed circuit board to facilitate a spot-plating process. In one embodiment, a printed circuit board substrate is provided which is at least partially conductive, such that a plating voltage may be applied to any one or more points on the substrate during a spot plating operation. In another embodiment, the substrate material is initially partially conductive, but following the spot-plating operation, is subjected to a curing treatment or the like to cause degeneration of the substrate's conductivity. Carbon-impregnated polyimide, partially-cured polyimide, FR4 or FR5, with appropriate contaminants introduced therein are contemplated as materials suitable for a printed circuit board substrate in accordance with the invention. In another embodiment, the traces are first applied to the partially conductive substrate by an electroplating operation wherein an electroplating voltage is applied to the substrate such that the substrate itself serves as one terminal of the electroplating system.
摘要翻译： 公开了一种用于印刷电路板迹线的选定区域的电解电镀的方法和装置。 该方法的特征在于消除了对印刷电路板上的母线和电镀触点的需要，以便于电镀过程。 在一个实施例中，提供至少部分导电的印刷电路板基板，使得可以在点电镀操作期间将电镀电压施加到基板上的任何一个或多个点。 在另一个实施例中，基板材料最初是部分导电的，但是在电镀操作之后，进行固化处理等以使基板导电性变差。 被浸入其中的合适污染物的碳浸渍的聚酰亚胺，部分固化的聚酰亚胺，FR4或FR5被考虑为适用于根据本发明的印刷电路板基底的材料。 在另一个实施例中，通过电镀操作首先将迹线施加到部分导电衬底上，其中将电镀电压施加到衬底，使得衬底本身用作电镀系统的一个端子。
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公开(公告)号：US06531345B2
公开(公告)日：2003-03-11
申请号：US09917695
申请日：2001-07-31
IPC分类号： H01L2182
CPC分类号： G11C29/88 , G11C5/063 , G11C29/006 , H01L22/22 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.
摘要翻译： 形成在相邻制造的电子设备之间的街道区域中的逻辑电路可以用作辅助或冗余组件来挽救一个或多个否则有缺陷的设备。 逻辑电路选择性地耦合到有缺陷的装置，以直接替换或促进在一个或多个制造的装置上更换有缺陷的部件，由此导致单个可操作的电子装置。 本发明可以用于增加电子设备，特别是半导体集成电路的生产成本。 本发明允许在半导体层的正常金属化期间制造任意布线，以在形成设备的正常布线/电路的同时互连电子器件。
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73.发明授权Device and method for testing integrated circuit dice in an integrated circuit module 失效在集成电路模块中测试集成电路芯片的装置和方法公开(公告)号：US06240535B1
公开(公告)日：2001-05-29
申请号：US09097427
申请日：1998-06-15
IPC分类号： G11C2900
CPC分类号： G11C29/785 , G01R31/2884 , G01R31/31701 , G01R31/31719 , G01R31/318513 , G11C29/1201 , G11C29/46 , G11C29/80 , G11C29/808 , H01L22/22 , H01L2224/48091 , H01L2224/48227 , H04J2203/0062 , H01L2924/00014
摘要： An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging. A method for performing such testing once the test mode has been initiated and for repairing any failing elements found during testing includes providing test signals to the dice, receiving response signals from the dice, evaluating the response signals to identify any failing elements in the dice, programming the failing elements' addresses into anti-fuses in the dice with a programming voltage, confirming that the addresses are programmed by determining the resistance of the anti-fuses, re-testing the dice, receiving response signals from the re-tested dice, and evaluating the response signals to confirm all repairs.
摘要翻译： 诸如多芯片模块（MCM）的IC模块包括多个IC芯片，每个具有测试模式使能焊盘，例如输出使能焊盘。 集成到MCM基板中的保险丝将每个管芯的测试模式使能接合焊盘连接到MCM的无连接（N / C）引脚之一，并且连接到衬底中的电阻将测试模式使能焊盘连接到MCM的一个接地 针脚。 通过向测试模式施加电源电压，使焊盘通过N / C引脚，在骰子中启动测试模式。 一旦测试完成，保险丝可能会被熔断，并且施加到测试模式的接地电压使得接合焊盘通过接地引脚，使得电阻器禁用骰子中的测试模式并启动操作模式。 因此，封装在IC模块中的裸片可以在封装后进行测试。 一旦测试模式已经启动并且用于修复在测试期间发现的任何故障元件，执行这种测试的方法包括向骰子提供测试信号，从骰子接收响应信号，评估响应信号以识别骰子中的任何故障元件， 使用编程电压将故障元件的地址编程为骰子中的防熔丝，确认通过确定防熔丝的电阻，重新测试骰子，从重新测试的骰子接收响应信号来编程地址， 并评估响应信号以确认所有维修。
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公开(公告)号：US5991904A
公开(公告)日：1999-11-23
申请号：US808392
申请日：1997-02-28
申请人： Kevin G. Duesman
发明人： Kevin G. Duesman
摘要： A circuit transfers data in an array of memory cells arranged in rows and columns. The circuit includes a plurality of row lines, a plurality of pairs of complementary digit lines, and an array of memory cells, each memory cell having a control terminal coupled to one of the row lines and a data terminal coupled to one of the complementary digit lines of one of the pairs of complementary digit lines responsive to a row enable signal on the row line of the row corresponding to the memory cell. A plurality of sense amplifiers are included in the circuit, each sense amplifier coupled to an associated pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and, in response to the sensed voltage differential, drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states. A plurality of equilibration circuits are also included in the circuit, each equilibration circuit coupled between one of the pairs of complementary digit lines and operable to equalize the voltage level on each pair of complementary digit lines to a predetermined level responsive to an equilibration signal. A control circuit is coupled to the plurality of row lines and the equilibration circuits. The control circuit is operable to: write a pattern of data to an initial row of the memory array; generate the equilibrate signal; apply a row enable signal to the row line of the memory cells in the initial row; terminate the row enable signal for the initial row; apply a row enable signal to the row line to which the memory cells in another row are connected; terminate the row enable signal for the another row; and generate the equilibrate signal.
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75.发明授权Circuit and method for measuring and forcing an internal voltage of an integrated circuit 失效用于测量和强制集成电路的内部电压的电路和方法
公开(公告)号：US5977763A
公开(公告)日：1999-11-02
申请号：US607688
申请日：1996-02-27
CPC分类号： G01R31/2884
摘要： A circuit (10) for reading a voltage at a voltage source (14) of an integrated circuit (12). In one version, the circuit (110) involves a pass circuit (118) that has an input coupled to the node (114) of the integrated circuit (12). The circuit (110) provides a measurement of the voltage at the node (114) as an output to a pin (116). A reset circuit (122) is coupled to the pass circuit (118) and is operable to activate and reset the pass circuit (118). Finally, a pass control circuit (120) is coupled to provide an output signal to the pass circuit (118) that drives the pass circuit (118) when active to pass the voltage at the node (114) to the pin (116).
摘要翻译： 一种用于读取集成电路（12）的电压源（14）处的电压的电路（10）。 在一个版本中，电路（110）涉及通过电路（118），其具有耦合到集成电路（12）的节点（114）的输入。 电路（110）提供节点（114）处的电压的测量作为针（116）的输出。 复位电路（122）耦合到通过电路（118）并且可操作以激活和复位通过电路（118）。 最后，当激活以将节点（114）处的电压传递到引脚（116）时，通过控制电路（120）被耦合以向传递电路（118）提供驱动通过电路（118）的输出信号。
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公开(公告)号：US5787044A
公开(公告)日：1998-07-28
申请号：US835867
申请日：1997-04-08
申请人： Kevin G. Duesman
发明人： Kevin G. Duesman
IPC分类号： G11C11/4074 , G11C29/00 , G11C1/40
CPC分类号： G11C29/832 , G11C11/4074 , G11C29/70
摘要： An array of memory cells are arranged in rows and columns. The array includes a plurality of cell plates that are each coupled to at least one of the memory cells. A generator produces a bias voltage. A plurality of isolation circuits are each coupled between the generator and one or more of the cell plates. Each isolation circuit provides the bias voltage to the cell plate or plates to which the isolation circuit is coupled. The cell plates may be coupled to memory cells from a plurality of the columns. Additionally, each of the isolation circuits may selectively provide, in response to a control signal, the bias voltage to the cell plate or plates to which the isolation circuit is coupled.
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77.再颁专利Inverting output driver circuit for reducing electron injection into the substrate 失效用于减少电子注入基板的反相输出驱动电路
公开(公告)号：USRE35764E
公开(公告)日：1998-04-07
申请号：US713757
申请日：1996-09-13
IPC分类号： H03K17/16 , H03K17/08 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0948 , H03K19/20
CPC分类号： H03K19/00361 , H03K19/00315
摘要： A new inverting output driver circuit is disclosed that reduces electron injection into the substrate by the drain of the circuit's pull-up field effect transistor. This is accomplished by adding additional circuitry that allows the gate voltage of the pull-up transistor to track the source voltage. The output circuit makes use of an inverter having an output node (hereinafter the intermediate node) coupled to V.sub.CC through a first P-channel FET, and to ground through first and second series coupled N-channel FETs, respectively. The gates of the P-channel FET and the first N-channel FET are coupled to and controlled by an input node. The inverter output node controls the gate of third N-channel FET, through which a final output node is coupled to V.sub.CC. The intermediate node is coupled to the final output node through a fourth N-channel FET, the gate of which is held at ground potential. The gate of the second N-channel FET is coupled to V.sub.CC through a second P-channel FET and to the final output node through a fifth N-channel FET which has much greater drive than the second P-channel FET; the gates of both the second P-channel FET and the fifth N-channel FET also being held at ground potential. Certain obvious variations of the circuit are possible. For example, the function of the first and second N-channel FETs may be reversed. In addition, the second P-channel FET functions as a resistor, and may be replaced with any device which functions as a resistor.
摘要翻译： 公开了一种新的反相输出驱动器电路，其通过电路的上拉场效应晶体管的漏极减少到衬底中的电子注入。 这是通过添加允许上拉晶体管的栅极电压跟踪源极电压的附加电路来实现的。 输出电路使用具有通过第一P沟道FET耦合到VCC的输出节点（以下称为中间节点）的逆变器，并且分别通过第一和第二串联耦合的N沟道FET接地。 P沟道FET和第一N沟道FET的栅极耦合到输入节点并由输入节点控制。 逆变器输出节点控制第三N沟道FET的栅极，最终的输出节点通过该栅极耦合到VCC。 中间节点通过第四N沟道FET耦合到最终输出节点，第四N沟道FET的栅极保持在地电位。 第二N沟道FET的栅极通过第二P沟道FET耦合到VCC，并通过具有比第二P沟道FET大得多的驱动的第五N沟道FET耦合到最终输出节点; 第二P沟道FET和第五N沟道FET两者的栅极也保持接地电位。 电路的某些明显变化是可能的。 例如，第一和第二N沟道FET的功能可以颠倒。 此外，第二P沟道FET用作电阻器，并且可以用用作电阻器的任何器件替代。
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公开(公告)号：US5539347A
公开(公告)日：1996-07-23
申请号：US393580
申请日：1995-02-23
申请人： Kevin G. Duesman
发明人： Kevin G. Duesman
CPC分类号： H03K17/22
摘要： A circuit, responsive to the application of primary power, generates signals to establish the initial state of a logic circuit. Generated signals are interposed on the logic circuit's input signal line until initialization is complete. After initialization, the logic circuit's input signal line is recoupled for normal operation.
摘要翻译： 响应于主电源的应用的电路产生信号以建立逻辑电路的初始状态。 生成的信号插入到逻辑电路的输入信号线上，直到初始化完成。 在初始化之后，逻辑电路的输入信号线被重新连接以进行正常操作。
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公开(公告)号：US20120001245A1
公开(公告)日：2012-01-05
申请号：US13231554
申请日：2011-09-13
IPC分类号： H01L27/108 , H01L27/105
CPC分类号： H01L29/66621 , H01L27/10876
摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.
摘要翻译： 公开了具有凹入式存取装置的半导体存储器件。 在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。 装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。 场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。 活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。
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80.发明授权Device and method for testing integrated circuit dice in an integrated circuit module 失效在集成电路模块中测试集成电路芯片的装置和方法公开(公告)号：US07730372B2
公开(公告)日：2010-06-01
申请号：US12233334
申请日：2008-09-18
IPC分类号： G01R31/28
CPC分类号： G11C29/785 , G01R31/2884 , G01R31/31701 , G01R31/31719 , G01R31/318513 , G11C29/1201 , G11C29/46 , G11C29/80 , G11C29/808 , H01L22/22 , H01L2224/48091 , H01L2224/48227 , H04J2203/0062 , H01L2924/00014
摘要： An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.
摘要翻译： 诸如多芯片模块（MCM）的IC模块包括多个IC芯片，每个具有测试模式使能焊盘，例如输出使能焊盘。 集成到MCM基板中的保险丝将每个管芯的测试模式使能接合焊盘连接到MCM的无连接（N / C）引脚之一，并且连接到衬底中的电阻将测试模式使能焊盘连接到MCM的一个接地 针脚。 通过向测试模式施加电源电压，使焊盘通过N / C引脚，在骰子中启动测试模式。 一旦测试完成，保险丝可能会被熔断，并且施加到测试模式的接地电压使得接合焊盘通过接地引脚，使得电阻器禁用骰子中的测试模式并启动操作模式。 因此，封装在IC模块中的裸片可以在封装后进行测试。
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