公开(公告)号：US20120256276A1

公开(公告)日：2012-10-11

申请号：US13082387

申请日：2011-04-07

申请人： Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

发明人： Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846

摘要： A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

摘要翻译： 提供一种制造金属栅极的方法。 该方法包括提供基板。 然后，在基板上形成栅极电介质层。 在栅极电介质层上形成具有功函数金属层的多层堆叠结构。 在多层堆叠结构的至少一层上进行O2气氛处理。 在多层堆叠结构上形成导电层。

公开(公告)号：US08252650B1

公开(公告)日：2012-08-28

申请号：US13092151

申请日：2011-04-22

申请人： Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

发明人： Feng-Yi Chang ,  Yi-Po Lin ,  Jiunn-Hsiung Liao ,  Shang-Yuan Tsai ,  Chih-Wen Feng ,  Shui-Yen Lu ,  Ching-Pin Hsu

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823864

摘要： A method for fabricating MOS transistor includes the steps of: overlapping a second stress layer on an etching stop layer and a first stress layer at a boundary region of the substrate; forming a dielectric layer on the first stress layer and the second stress layer; performing a first etching process to partially remove the dielectric layer for exposing a portion of the second stress layer at the boundary region; performing a second etching process to partially remove the exposed portion of the second stress layer for exposing the etching stop layer; performing a third etching process to partially remove the exposed portion of the etching stop layer for exposing the first stress layer at the boundary region; and performing a fourth etching process partially remove the exposed portion of the first stress layer.

摘要翻译： 一种用于制造MOS晶体管的方法包括以下步骤：在蚀刻停止层和基板的边界区域处的第一应力层上重叠第二应力层; 在所述第一应力层和所述第二应力层上形成介电层; 执行第一蚀刻工艺以部分去除所述电介质层以暴露所述边界区域处的所述第二应力层的一部分; 执行第二蚀刻工艺以部分地去除第二应力层的暴露部分以暴露蚀刻停止层; 执行第三蚀刻工艺以部分地去除用于在边界区域露出第一应力层的蚀刻停止层的暴露部分; 并且执行第四蚀刻工艺部分地去除第一应力层的暴露部分。

公开(公告)号：US08071487B2

公开(公告)日：2011-12-06

申请号：US11464496

申请日：2006-08-15

申请人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Jiunn-Hsiung Liao ,  Min-Chieh Yang ,  Chuan-Kai Wang

发明人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Jiunn-Hsiung Liao ,  Min-Chieh Yang ,  Chuan-Kai Wang

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/0271 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/32139

摘要： A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer is between the underlayer and the photoresist layer. The thickness of the photoresist layer is smaller than that of the underlayer and larger than two times of the thickness of the silicon rich organic layer. The thickness of the underlayer is smaller than three times of the predetermined opening width.

摘要翻译： 提供了用于图案化材料层以形成在该层中具有预定开口宽度的开口图案的层叠结构。 层叠结构包括底层，富硅有机层和光致抗蚀剂层。 底层在材料层上。 富硅有机层位于底层和光刻胶层之间。 光致抗蚀剂层的厚度小于底层的厚度，并且大于富硅有机层的厚度的两倍。 底层的厚度小于预定开口宽度的三倍。

公开(公告)号：US20110254142A1

公开(公告)日：2011-10-20

申请号：US13167737

申请日：2011-06-24

申请人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Jiunn-Hsiung Liao ,  Min-Chieh Yang ,  Chuan-Kai Wang

发明人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Jiunn-Hsiung Liao ,  Min-Chieh Yang ,  Chuan-Kai Wang

IPC分类号： H01L29/02

CPC分类号： H01L21/0271 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/32139

摘要： A stacked structure for patterning a material layer to form an opening pattern with a predetermined opening width in the layer is provided. The stacked structure includes an underlayer, a silicon rich organic layer, and a photoresist layer. The underlayer is on the material layer. The silicon rich organic layer is between the underlayer and the photoresist layer. The thickness of the photoresist layer is smaller than that of the underlayer and larger than two times of the thickness of the silicon rich organic layer. The thickness of the underlayer is smaller than three times of the predetermined opening width.

摘要翻译： 提供了用于图案化材料层以形成在该层中具有预定开口宽度的开口图案的层叠结构。 层叠结构包括底层，富硅有机层和光致抗蚀剂层。 底层在材料层上。 富硅有机层位于底层和光刻胶层之间。 光致抗蚀剂层的厚度小于底层的厚度，并且大于富硅有机层的厚度的两倍。 底层的厚度小于预定开口宽度的三倍。

公开(公告)号：US07799511B2

公开(公告)日：2010-09-21

申请号：US11696194

申请日：2007-04-04

申请人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Jiunn-Hsiung Liao

IPC分类号： G03F7/26

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338

摘要： A method of forming a contact hole is provided. A pattern is formed in a photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a first opening. Another pattern is formed in another photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a second opening. The pattern having the first, and second openings is exchanged into the interlayer dielectric layer, and etching stop layer to form the contact hole. The present invention has twice exposure processes and twice etching processes to form the contact hole having small distance.

摘要翻译： 提供一种形成接触孔的方法。 在光致抗蚀剂层中形成图案。 将图案交换成硅光致抗蚀剂层以形成第一开口。 在另一光致抗蚀剂层中形成另一图案。 将图案交换为硅光致抗蚀剂层以形成第二开口。 将具有第一和第二开口的图案交换到层间电介质层和蚀刻停止层以形成接触孔。 本发明具有两次曝光工艺和两次蚀刻工艺以形成具有小距离的接触孔。

公开(公告)号：US07687446B2

公开(公告)日：2010-03-30

申请号：US11307394

申请日：2006-02-06

申请人： Cheng-Ming Weng ,  Miao-Chun Lin ,  Mei-Chi Wang ,  Jiunn-Hsiung Liao ,  Wei-Cheng Yang

发明人： Cheng-Ming Weng ,  Miao-Chun Lin ,  Mei-Chi Wang ,  Jiunn-Hsiung Liao ,  Wei-Cheng Yang

IPC分类号： H01L21/02

CPC分类号： C11D7/08 ,  C11D7/265 ,  C11D11/0047 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/76814

摘要： A method of removing the residue left after a plasma process is described. First, a substrate having at least a material layer thereon is provided. The material layer includes a metal. Then, a fluorine-containing plasma process is performed so that a residue containing the aforesaid metallic material is formed on the surface of the material layer. After that, a wet cleaning operation is performed using a cleaning agent to remove the residue. The cleaning agent is a solution containing water, a diluted hydrofluoric acid and an acid solution.

摘要翻译： 描述了在等离子体处理之后留下残留物的方法。 首先，提供至少具有材料层的基板。 材料层包括金属。 然后，进行含氟等离子体处理，使得在材料层的表面上形成含有上述金属材料的残渣。 之后，使用清洁剂进行湿式清洗操作以除去残留物。 清洗剂是含有水，稀释的氢氟酸和酸溶液的溶液。

公开(公告)号：US20090081817A1

公开(公告)日：2009-03-26

申请号：US11860792

申请日：2007-09-25

申请人： Lung-En Kuo ,  Jiunn-Hsiung Liao ,  Min-Chieh Yang

发明人： Lung-En Kuo ,  Jiunn-Hsiung Liao ,  Min-Chieh Yang

IPC分类号： H01L21/66

CPC分类号： H01L21/76224 ,  H01L22/26

摘要： A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.

摘要翻译： 提供了图案化方法。 在图案化方法中，在基板上形成膜，并测量预层信息。 接下来，进行蚀刻处理以蚀刻该膜。 蚀刻工艺包括主蚀刻步骤，蚀刻终点检测步骤，延伸蚀刻步骤和过蚀刻步骤。 基于预定的延长蚀刻时间和预层信息之间的相关性，在10秒钟内设定用于进行延长蚀刻步骤的延长蚀刻时间，以便获得所需的膜轮廓。

公开(公告)号：US20090045456A1

公开(公告)日：2009-02-19

申请号：US11837746

申请日：2007-08-13

申请人： Hsuan-Hsu Chen ,  Hsin-Chi Chen ,  Jiunn-Hsiung Liao

发明人： Hsuan-Hsu Chen ,  Hsin-Chi Chen ,  Jiunn-Hsiung Liao

IPC分类号： H01L31/0312 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/3085 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

摘要： A method of fabricating a semiconductor device is provided. The method includes forming a gate structure on a substrate. The gate structure includes a patterned gate dielectric layer, a patterned gate conductor layer, a cap layer and a spacer. Next, a first and a second recesses are formed in the substrate on the two sides of the gate structure. Thereafter, a protection layer is formed on the bottom surfaces of the first and the second recesses, and then a etching process is performed to laterally enlarge first and the second recesses towards the direction of the gate structure. Thereafter, a material layer is respectively formed in the first recess and the second recess. Afterward, two source/drain contact regions are respectively formed in the material layers of the first recess and the second recess.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成栅极结构。 栅极结构包括图案化栅极介电层，图案化栅极导体层，盖层和间隔物。 接下来，在栅极结构的两侧上的基板中形成第一和第二凹部。 此后，在第一凹部和第二凹部的底面上形成保护层，然后进行蚀刻处理，以朝向栅极结构的方向横向放大第一凹部和第二凹部。 此后，在第一凹部和第二凹部中分别形成材料层。 之后，在第一凹部和第二凹部的材料层中分别形成两个源极/漏极接触区域。

公开(公告)号：US20080164526A1

公开(公告)日：2008-07-10

申请号：US11620028

申请日：2007-01-04

申请人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Min-Chieh Yang ,  Jiunn-Hsiung Liao

发明人： Meng-Jun Wang ,  Yi-Hsing Chen ,  Min-Chieh Yang ,  Jiunn-Hsiung Liao

IPC分类号： H01L29/786 ,  G03F1/00 ,  H01L21/283

CPC分类号： H01L21/28123 ,  H01L21/0271 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/7624 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/947 ,  Y10S438/95

摘要： A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.

摘要翻译： 提供了修剪硬掩模的方法。 该方法包括在衬底上提供衬底，硬掩模层和三层堆叠。 三层堆叠包括顶部光致抗蚀剂层，硅光致抗蚀剂层和底部光致抗蚀剂层。 顺序地对顶部光致抗蚀剂层，硅光致抗蚀剂层，底部光致抗蚀剂层和硬掩模层进行图案化。 在硬掩模层上进行修整处理。 本发明的底部光致抗蚀剂层在蚀刻工艺中更薄并且损失一些高度，因此底部光致抗蚀剂层将不会塌陷。

公开(公告)号：US20080064203A1

公开(公告)日：2008-03-13

申请号：US11530886

申请日：2006-09-11

申请人： Pei-Yu Chou ,  Wen-Chou Tsai ,  Jiunn-Hsiung Liao

发明人： Pei-Yu Chou ,  Wen-Chou Tsai ,  Jiunn-Hsiung Liao

IPC分类号： H01L21/467

CPC分类号： H01L21/76802 ,  H01L21/0271 ,  H01L21/0338 ,  H01L21/31138 ,  H01L21/31144

摘要： A method for fabricating a contact hole is provided. A semiconductor substrate having thereon a conductive region is prepared. A dielectric layer is deposited on the semiconductor substrate and the conductive region. An etching resistive layer is coated on the dielectric layer. A silicon-containing hard mask bottom anti-reflection coating (SHB) layer is then coated on the etching resistive layer. A photoresist layer is then coated on the SHB layer. A lithographic process is performed to form a first opening in the photoresist layer. Using the photoresist layer as a hard mask, the SHB layer is etched through the first opening, thereby forming a shrunk, tapered second opening in the SHB layer. Using the etching resistive layer as an etching hard mask, etching the dielectric layer through the second opening to form a contact hole in the dielectric layer.

摘要翻译： 提供一种制造接触孔的方法。 制备其上具有导电区域的半导体衬底。 介电层沉积在半导体衬底和导电区域上。 在电介质层上涂覆有蚀刻电阻层。 然后将含硅硬掩模底部防反射涂层（SHB）层涂覆在蚀刻电阻层上。 然后将光致抗蚀剂层涂覆在SHB层上。 执行光刻工艺以在光致抗蚀剂层中形成第一开口。 使用光致抗蚀剂层作为硬掩模，通过第一开口蚀刻SHB层，从而在SHB层中形成收缩的锥形第二开口。 使用蚀刻电阻层作为蚀刻硬掩模，通过第二开口蚀刻电介质层，以在电介质层中形成接触孔。