公开(公告)号：US20090101956A1

公开(公告)日：2009-04-23

申请号：US11873728

申请日：2007-10-17

申请人： Roger A. Booth, JR. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

发明人： Roger A. Booth, JR. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

IPC分类号： H01L27/108 ,  H01G4/00 ,  H01L21/8242

CPC分类号： H01L27/1087

摘要： A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region.

摘要翻译： 在半导体衬底和衬垫层中形成深沟槽，并填充有虚拟节点电介质和虚设沟槽填充物。 在半导体衬底中形成浅沟槽隔离结构。 去除焊盘层之后，在器件区域中形成虚拟栅极结构。 在虚拟栅极结构上形成第一电介质层，并且填充虚拟沟槽的突出部分，然后进行平坦化。 虚拟结构被去除。 深沟槽和通过去除伪栅极结构形成的空腔填充有高介电常数材料层和金属层，其形成深沟槽中的高k节点电介质和深沟槽电容器的金属内电极 以及在器件区域中的高k栅极电介质和金属栅极。

公开(公告)号：US20090051002A1

公开(公告)日：2009-02-26

申请号：US11843047

申请日：2007-08-22

申请人： Roger A. Booth, JR. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

发明人： Roger A. Booth, JR. ,  MaryJane Brodsky ,  Kangguo Cheng ,  Chengwen Pei

IPC分类号： H01L29/00 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses.

摘要翻译： 薄半导体层在半导体衬底上形成并图案化以在浅沟槽隔离上以及在阳极半导体区域和阴极半导体区域之间形成薄的半导体熔丝。 在金属化期间，由于半导体软管中的所有半导体材料与金属反应而形成金属半导体合金，所以将半导体熔融金属转换为薄金属半导体合金熔丝。 本发明的电熔丝包括薄金属半导体合金熔丝，金属半导体合金阳极和金属半导体合金阴极。 与现有技术的电熔丝相比，薄金属半导体合金熔体具有较小的横截面积。 与现有技术的电熔丝相比，可以获得与现有技术的电熔丝相当的在熔丝中的电流密度和在熔丝与阴极或阳极之间的界面处的电流发散度，而不是现有技术的电熔丝。

公开(公告)号：US09076817B2

公开(公告)日：2015-07-07

申请号：US13198152

申请日：2011-08-04

申请人： Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L29/66 ,  H01L29/51

CPC分类号： H01L29/6656 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.

摘要翻译： 通过在半导体层上形成围绕栅极结构的第一深度的一对第一沟槽，在半导体层中形成一对水平台阶包含的沟槽，在栅极结构周围形成一次性间隔物，以覆盖第一 并且通过形成大于第一深度的第二深度的一对第二沟槽。 去除一次性间隔物，并进行选择性外延以形成集成的外延源和源极延伸区域以及集成的外延漏极和漏极延伸区域。 可以在平坦化介电层的沉积和平坦化之后形成替代栅极结构，并且随后去除栅极结构并且在外延源极和漏极延伸区域上横向扩展栅极腔。 或者，可以将接触电介质层直接沉积在集成的外延区上，并且可以在其中形成接触通孔结构。

公开(公告)号：US08637958B2

公开(公告)日：2014-01-28

申请号：US13617576

申请日：2012-09-14

申请人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi Todi ,  Geng Wang

发明人： Abhishek Dube ,  Subramanian S. Iyer ,  Babar Ali Khan ,  Oh-jung Kwon ,  Junedong Lee ,  Paul C. Parries ,  Chengwen Pei ,  Gerd Pfeiffer ,  Ravi Todi ,  Geng Wang

IPC分类号： H01L21/02

CPC分类号： H01L29/945 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/66181

摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.

摘要翻译： 公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。 该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区。 该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

公开(公告)号：US08507915B2

公开(公告)日：2013-08-13

申请号：US13307787

申请日：2011-11-30

申请人： Karen A. Nummy ,  Chengwen Pei ,  Werner A. Rausch ,  Geng Wang

发明人： Karen A. Nummy ,  Chengwen Pei ,  Werner A. Rausch ,  Geng Wang

IPC分类号： H01L29/94

CPC分类号： H01L21/4846 ,  H01L21/82 ,  H01L27/10867 ,  H01L29/66181 ,  H01L29/66636 ,  H01L29/945

摘要： A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode.

公开(公告)号：US20130032868A1

公开(公告)日：2013-02-07

申请号：US13198100

申请日：2011-08-04

申请人： Chengwen Pei ,  Xi Li ,  Geng Wang

发明人： Chengwen Pei ,  Xi Li ,  Geng Wang

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L29/0692 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.

摘要翻译： 公开了一种沟槽电容器和制造方法。 掺杂SOI区域使得用于沟槽加宽的选择性各向同性蚀刻不会导致SOI区域的明显的回退，并且在沟槽的上部不需要间隔物。

公开(公告)号：US08354675B2

公开(公告)日：2013-01-15

申请号：US12775532

申请日：2010-05-07

申请人： Oh-jung Kwon ,  Junedong Lee ,  Chengwen Pei ,  Geng Wang

发明人： Oh-jung Kwon ,  Junedong Lee ,  Chengwen Pei ,  Geng Wang

IPC分类号： H01L27/108

CPC分类号： H01L28/82 ,  H01L27/10867 ,  H01L29/66181

摘要： A substrate including a stack of a handle substrate, an optional lower insulator layer, a doped polycrystalline semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. A deep trench is formed through the top semiconductor layer, the upper insulator layer, and the doped polycrystalline semiconductor layer. Exposed vertical surfaces of the polycrystalline semiconductor layer are crystallographically etched to form random facets in the deep trench, thereby increasing the total exposed surface area of the polycrystalline semiconductor layer in the deep trench. A node dielectric and at least one conductive material are deposited to fill the trench and to form a buried strap portion, which constitute a capacitor of an eDRAM. Access transistors and other logic devices can be formed.

摘要翻译： 提供了包括手柄衬底，可选的下绝缘体层，掺杂多晶半导体层，上绝缘体层和顶部半导体层的衬底的衬底。 通过顶部半导体层，上部绝缘体层和掺杂多晶半导体层形成深沟槽。 多晶半导体层的暴露的垂直表面被晶体学蚀刻以在深沟槽中形成随机刻面，从而增加深沟槽中的多晶半导体层的总暴露表面积。 沉积节点电介质和至少一种导电材料以填充沟槽并形成构成eDRAM的电容器的掩埋带部分。 可以形成存取晶体管和其它逻辑器件。

公开(公告)号：US08809953B2

公开(公告)日：2014-08-19

申请号：US13426547

申请日：2012-03-21

申请人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

发明人： David M. Fried ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

摘要： A field effect transistor (FET) structure on a semiconductor substrate which includes a gate structure having a spacer on a semiconductor substrate; an extension implant underneath the gate structure; a recessed source and a recessed drain filled with a doped epitaxial material; halo implanted regions adjacent a bottom of the recessed source and drain and being underneath the gate stack. In an exemplary embodiment, there is implanted junction butting underneath the bottom of each of the recessed source and drain, the junction butting being separate and distinct from the halo implanted regions. In another exemplary embodiment, the doped epitaxial material is graded from a lower dopant concentration at a side of the recessed source and drain to a higher dopant concentration at a center of the recessed source and drain. In a further exemplary embodiment, the semiconductor substrate is a semiconductor on insulator substrate.

摘要翻译： 一种半导体衬底上的场效应晶体管（FET）结构，其包括在半导体衬底上具有间隔物的栅极结构; 栅极结构下面的延伸植入物; 凹陷的源极和填充有掺杂的外延材料的凹陷的漏极; 邻近凹陷源的底部的卤素注入区域和漏极并位于栅极叠层下方。 在示例性实施例中，在凹陷源和漏极中的每一个的底部下方注入结合对接，该接合部分与光晕注入区域分开且不同。 在另一个示例性实施例中，掺杂的外延材料从凹陷源的一侧的较低掺杂剂浓度和漏极分级到凹陷源极和漏极的中心处的较高掺杂剂浓度。 在另一示例性实施例中，半导体衬底是绝缘体上半导体衬底。

公开(公告)号：US20130134491A1

公开(公告)日：2013-05-30

申请号：US13307874

申请日：2011-11-30

申请人： Brian W. Messenger ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Brian W. Messenger ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L27/108 ,  H01L21/02

CPC分类号： H01L27/10829 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a trench structure that includes forming a metal containing layer on at least the sidewalls of a trench, and forming an undoped semiconductor fill material within the trench. The undoped semiconductor fill material and the metal containing layer are recessed to a first depth within the trench with a first etch. The undoped semiconductor fill material is then recessed to a second depth within the trench that is greater than a first depth with a second etch. The second etch exposes at least a sidewall portion of the metal containing layer. The trench is filled with a doped semiconductor containing material fill, wherein the doped semiconductor material fill is in direct contact with the at least the sidewall portion of the metal containing layer.

摘要翻译： 一种形成沟槽结构的方法，其包括在至少沟槽的侧壁上形成含金属层，以及在所述沟槽内形成未掺杂的半导体填充材料。 未掺杂的半导体填充材料和含金属层通过第一蚀刻凹陷到沟槽内的第一深度。 然后将未掺杂的半导体填充材料凹入到沟槽内的第二深度，其大于具有第二蚀刻的第一深度。 第二蚀刻暴露了含金属层的至少一个侧壁部分。 沟槽填充有掺杂的半导体含有材料填充物，其中掺杂半导体材料填充物与含金属层的至少侧壁部分直接接触。

公开(公告)号：US08470684B2

公开(公告)日：2013-06-25

申请号：US13106349

申请日：2011-05-12

申请人： Chengwen Pei ,  Geng Wang

发明人： Chengwen Pei ,  Geng Wang

IPC分类号： H01L21/20

CPC分类号： H01L29/66181 ,  H01L21/2652 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10897 ,  H01L29/945

摘要： Dopants of a first conductivity type are implanted into a top portion of a semiconductor substrate having a doping of the first conductivity type to increase the dopant concentration in the top portion, which is a first-conductivity-type semiconductor layer. A semiconductor material layer having a doping of the second conductivity type, a buried insulator layer, and a top semiconductor layer are formed thereupon. Deep trenches having a narrow width have a bottom surface within the second-conductivity-type semiconductor layer, which functions as a buried plate. Deep trenches having a wider width are etched into the first-conductivity-type layer underneath, and can be used to form an isolation structure. The additional dopants in the first-conductivity-type semiconductor layer provide a counterdoping against downward diffusion of dopants of the second conductivity type to enhance electrical isolation.

摘要翻译： 将第一导电类型的掺杂剂注入到具有第一导电类型的掺杂的半导体衬底的顶部中，以增加作为第一导电型半导体层的顶部中的掺杂剂浓度。 在其上形成具有第二导电类型的掺杂的半导体材料层，掩埋绝缘体层和顶部半导体层。 具有窄宽度的深沟槽具有在第二导电型半导体层内的底表面，其用作掩埋板。 具有较宽宽度的深沟槽被蚀刻到下面的第一导电类型层中，并且可用于形成隔离结构。 第一导电型半导体层中的附加掺杂剂提供反向掺杂以抵抗第二导电类型的掺杂剂的向下扩散以增强电隔离。