公开(公告)号：US20100110763A1

公开(公告)日：2010-05-06

申请号：US12426098

申请日：2009-04-17

申请人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

发明人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C8/08 ,  G11C11/416

CPC分类号： G11C8/08 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0071

摘要： Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.

摘要翻译： 非易失性存储单元中的写入电流补偿的装置和方法，例如但不限于自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM）。 根据一些实施例，非易失性存储器单元具有耦合到开关器件的电阻感测元件（RSE），RSE具有硬编程方向和与硬编程方向相反的简单编程方向。 升压电路包括电容器，该电容器将电压加到由电压源向节点提供的标称非零电压以产生暂时提升的电压。 当RSE在硬编程方向编程时，升压电压施加到开关器件。

公开(公告)号：US20100095052A1

公开(公告)日：2010-04-15

申请号：US12482693

申请日：2009-06-11

申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Yuan Yan ,  Harry Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Yuan Yan ,  Harry Hongyue Liu

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F12/0246 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/225 ,  G06F2212/7202

摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector.

摘要翻译： 本发明的各种实施例通常涉及用于更新非易失性存储器阵列中的数据的装置和相关联的方法。 根据一些实施例，存储器块形成有布置在第一类型的数据页中的多种类型的存储器单元扇区和可以就地更新的第二类型的日志页。 将第一更新的扇区写入第一日志页面，同时保持原始数据页面中的过时扇区，并被第二更新扇区覆盖。

公开(公告)号：US08934281B2

公开(公告)日：2015-01-13

申请号：US13274876

申请日：2011-10-17

申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C11/56 ,  G11C13/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069

摘要： Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.

摘要翻译： 本发明的各种实施例一般涉及一种用于为电阻式感测存储器（RSM）阵列提供不同的比特设置模式的方法和装置，诸如自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM） ）数组。 根据一些实施例，识别非易失性半导体存储器阵列中的一组RSM单元用于位设置操作的应用。 从对RSM单元分别写入的多个位设置值中选择位设置值，以将所述单元置于选择的电阻状态。 所选位设定值此后被写入所识别的组中的RSM单元的至少一部分。

公开(公告)号：US08289752B2

公开(公告)日：2012-10-16

申请号：US13353354

申请日：2012-01-19

申请人： Yong Lu ,  Harry Hongyue Liu

发明人： Yong Lu ,  Harry Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/79

摘要： Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.

摘要翻译： 用于电阻感测存储器（RSM）单元的非对称写入电流补偿的装置和相关方法，例如但不限于自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM）单元。 根据一些实施例，RSM单元包括耦合到开关装置的RSM元件。 开关装置具有多个端子。 控制电路通过限制端子两端的电压差的范围来补偿RSM单元的不对称写入特性，以便等于或小于施加到开关器件的源极电压的幅度，由此提供双向写入电流 通过RSM元件具有基本相等的幅度。

公开(公告)号：US08203899B2

公开(公告)日：2012-06-19

申请号：US12946582

申请日：2010-11-15

申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Harry Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Harry Hongyue Liu

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2207/063

摘要： Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second read current is subsequently applied to the memory cell to generate a second voltage, with the second read current being proportional in magnitude to the first read current. A comparison is made between the first and second voltages to determine the programmed state of the memory cell.

摘要翻译： 本发明的各种实施例通常涉及用于感测诸如自旋扭矩传递随机存取存储器（STRAM）单元的存储器单元的编程状态的方法和装置。 将第一读取电流施加到存储器单元以产生第一电压。 随后将第二读取电流施加到存储器单元以产生第二电压，其中第二读取电流在幅度上与第一读取电流成比例。 在第一和第二电压之间进行比较以确定存储器单元的编程状态。

公开(公告)号：US08203862B2

公开(公告)日：2012-06-19

申请号：US12502191

申请日：2009-07-13

申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Yuan Yan ,  Harry Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Yuan Yan ,  Harry Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： G11C7/14 ,  G11C5/147 ,  G11C11/1673

摘要： An apparatus and associated method for generating a reference voltage with dummy resistive sense element regions. A first resistance distribution is obtained for a first dummy region of resistance sense elements and a second resistance distribution is obtained for a second dummy region of resistive sense elements. A user resistive sense element from a user region is assigned to a selected resistive sense element of one of the first or second dummy regions in relation to the first and second resistance distributions.

摘要翻译： 一种用于产生具有虚拟电阻感测元件区域的参考电压的装置和相关联的方法。 对于电阻感测元件的第一虚拟区域获得第一电阻分布，并且获得电阻感测元件的第二虚拟区域的第二电阻分布。 来自用户区域的用户电阻感测元件相对于第一和第二电阻分布被分配给第一或第二虚拟区域中的一个的所选择的电阻感测元件。

公开(公告)号：US08194437B2

公开(公告)日：2012-06-05

申请号：US12352713

申请日：2009-01-13

申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

IPC分类号： G11C11/44

CPC分类号： G11C11/22

摘要： Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces.

摘要翻译： 各种实施例通常涉及与操作具有多个接口和状态寄存器的第一存储器件相关联的方法和装置。 在一些实施例中，主机接合第一接口。 具有由至少磁性隧道结和自旋极化磁性材料构成的多个存储单元的存储器件连接到第二接口。 通过在数据传输操作期间通过第一和第二接口记录至少一个错误或忙信号来维护状态寄存器。

公开(公告)号：US20120120713A1

公开(公告)日：2012-05-17

申请号：US13353354

申请日：2012-01-19

申请人： Yong Lu ,  Harry Hongyue Liu

发明人： Yong Lu ,  Harry Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/79

摘要： Apparatus and associated method for asymmetric write current compensation for resistive sense memory (RSM) cells, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) cells. In accordance with some embodiments, an RSM cell includes an RSM element coupled to a switching device. The switching device has a plurality of terminals. A control circuit compensates for asymmetric write characteristics of the RSM cell by limiting a range of voltage differentials across the terminals so as to be equal to or less than a magnitude of a source voltage applied to the switching device, thereby providing bi-directional write currents of substantially equal magnitude through the RSM element.

摘要翻译： 用于电阻感测存储器（RSM）单元的非对称写入电流补偿的装置和相关方法，例如但不限于自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM）单元。 根据一些实施例，RSM单元包括耦合到开关装置的RSM元件。 开关装置具有多个端子。 控制电路通过限制端子两端的电压差的范围来补偿RSM单元的不对称写入特性，以便等于或小于施加到开关器件的源极电压的幅度，由此提供双向写入电流 通过RSM元件具有基本相等的幅度。

公开(公告)号：US20110299324A1

公开(公告)日：2011-12-08

申请号：US13210934

申请日：2011-08-16

申请人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

发明人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0071

摘要： Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.

摘要翻译： 非易失性存储单元中的写入电流补偿的装置和方法，例如但不限于自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM）。 根据一些实施例，非易失性存储器单元具有耦合到开关器件的电阻感测元件（RSE），RSE具有硬编程方向和与硬编程方向相反的简单编程方向。 升压电路包括电容器，该电容器将电压加到由电压源向节点提供的标称非零电压以产生暂时提升的电压。 当RSE在硬编程方向编程时，升压电压施加到开关器件。

公开(公告)号：US08040713B2

公开(公告)日：2011-10-18

申请号：US12352693

申请日：2009-01-13

申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069

摘要： Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.

摘要翻译： 本发明的各种实施例一般涉及一种用于为电阻式感测存储器（RSM）阵列提供不同的比特设置模式的方法和装置，诸如自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM） ）数组。 根据一些实施例，识别非易失性半导体存储器阵列中的一组RSM单元用于位设置操作的应用。 从对RSM单元分别写入的多个位设置值中选择位设置值，以将所述单元置于选择的电阻状态。 所选位设定值此后被写入所识别的组中的RSM单元的至少一部分。