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公开(公告)号：US20070238278A1
公开(公告)日：2007-10-11
申请号：US11278180
申请日：2006-03-31
IPC分类号： H01L21/3205
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L29/6653 , H01L29/66825 , H01L29/66833
摘要： Removing a portion of a structure in a semiconductor device to separate the structure. The structure has two portions of different heights. In one example, the structure is removed by forming a spacer over the lower portion adjacent to the sidewall of the higher portion. A second material is then formed on the structure outside of the spacer. The spacer is removed and the portion under the spacer is then removed to separate the structure at that location. In one embodiment, separate channel regions are implemented in the separated structures. In other embodiments, separate gate structures are implemented in the separated structures.
摘要翻译： 去除半导体器件中的一部分结构以分离结构。 该结构具有两个不同高度的部分。 在一个示例中，通过在与较高部分的侧壁相邻的下部形成隔离物来移除结构。 然后在间隔件外部的结构上形成第二材料。 移除间隔物，然后移除间隔物下面的部分以在该位置分离结构。 在一个实施例中，在分离的结构中实现单独的通道区域。 在其他实施例中，在分离的结构中实现单独的门结构。
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72.发明申请Electronic devices including non-volatile memory and processes for forming the same 有权包括非易失性存储器的电子设备及其形成工艺公开(公告)号：US20060211206A1
公开(公告)日：2006-09-21
申请号：US11084283
申请日：2005-03-18
IPC分类号： H01L21/8234 , H01L21/76
CPC分类号： H01L27/11526 , B82Y10/00 , H01L27/105 , H01L27/11546
摘要： A process for forming an electronic device can be performed, such that as little as one gate electric layer may be formed within each region of the electronic device. In one embodiment, the electronic device can include an NVM array and other regions that have different gate dielectric layers. By protecting the field isolation regions within the NVM array and other regions while gate dielectric layer are formed, the field isolation regions may be exposed to as little as one oxide etch between the time any of the gate dielectric layers are formed the time such gate dielectric layers are covered by gate electrode layers. The process helps to reduce field isolation erosion and reduce problems associated therewith.
摘要翻译： 可以执行用于形成电子器件的工艺，使得可以在电子器件的每个区域内形成少至一个栅极电层。 在一个实施例中，电子设备可以包括NVM阵列和具有不同栅介电层的其它区域。 通过在形成栅介质层的同时保护NVM阵列和其它区域内的场隔离区域，在形成任何栅极电介质层的时间之间，场隔离区可能暴露于少至一个氧化物蚀刻， 层被栅极电极层覆盖。 该过程有助于减少场隔离侵蚀并减少与之相关的问题。
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公开(公告)号：US20060211199A1
公开(公告)日：2006-09-21
申请号：US11082094
申请日：2005-03-16
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/30604 , H01L21/3065 , H01L29/42332 , H01L29/66825
摘要： A method for removing nanoclusters from a semiconductor device includes etching a selected portion of an insulating layer, flowing a reducing gas over the semiconductor device at a temperature in a range of 400-900 degrees Celsius, and flowing a gas comprising halogen over the semiconductor device a temperature in a range of 400-900 degrees Celsius. In another form, a method for removing the nanoclusters includes implanting germanium or nitrogen into the nanoclusters, etching a selected portion of the insulating layer using a dry etch process, and removing the layer of nanoclusters using a wet etch process that is selective to an insulating layer.
摘要翻译： 一种用于从半导体器件中去除纳米团簇的方法包括：在400-900摄氏度的温度范围内蚀刻绝缘层的选定部分，使还原气体在半导体器件上流动，并使包含卤素的气体流过半导体器件 温度在400-900摄氏度的范围内。 在另一种形式中，用于去除纳米团簇的方法包括将锗或氮注入到纳米团簇中，使用干蚀刻工艺蚀刻绝缘层的选定部分，以及使用对绝缘选择性的湿蚀刻工艺去除纳米团簇层 层。
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74.发明授权公开(公告)号：US07109550B2
公开(公告)日：2006-09-19
申请号：US11036860
申请日：2005-01-13
IPC分类号： H01L29/792
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823468 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/7842 , Y10S257/90
摘要： A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.
摘要翻译： 半导体工艺和所得晶体管包括在栅电极（116）的任一侧上形成导电延伸间隔物（146,150）。 导电延伸部（146,150）和栅电极116被独立地掺杂，使得每个结构可以是n型或p型。 源极/漏极区域（156）被植入在间隔物（146,150）的任一侧上。 间隔物（146,150）可以通过使用第一成角度的植入物（132）来掺杂第一延伸间隔物（146）和第二成角度的植入物（140）以掺杂第二间隔物（150）来独立地掺杂。 在一个实施例中，使用不同掺杂的延伸间隔物（146,150）消除了对阈值调整通道植入物的需要。
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公开(公告)号：US20060194438A1
公开(公告)日：2006-08-31
申请号：US10876820
申请日：2004-06-25
IPC分类号： H01L21/302 , H01L31/112 , H01L21/36
CPC分类号： H01L27/11546 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L27/11573 , H01L29/42332
摘要： A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.
摘要翻译： 通过使用覆盖纳米团簇的中间双重多晶氮化物控制电极堆叠形成多个存储单元器件。 堆叠包括第一形成的多晶氮化物层和第二形成的含多晶硅的层。 第二形成的含多晶硅的层从包含多个存储单元的区域中去除。 在一种形式中，第二形成的含多晶硅的层还包含也被去除的氮化物部分，从而留下用于存储单元器件的第一形成的多晶氮化物层。 在另一种形式中，第二形成的含硅层不含有氮化物，并且还去除了第一形成的多晶氮化物层的氮化物部分。 在后一种形式中，在剩余的多晶硅层上形成随后的氮化物层。 在这两种形式中，器件的顶部部分被保护免受氧化，从而保持下面的纳米簇的尺寸和质量。 存储单元器件外围的器件的栅电极也使用第二形成的含多晶硅的层。
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公开(公告)号：US20060189079A1
公开(公告)日：2006-08-24
申请号：US11065519
申请日：2005-02-24
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , B82Y10/00 , H01L29/40114 , H01L29/66825
摘要： A method for forming nanoclusters includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate, exposing the semiconductor substrate to a first flux of atoms to form first nuclei on the dielectric layer, exposing the first nuclei to a first inert atmosphere after exposing the semiconductor substrate to the first flux, and exposing the semiconductor substrate to a second flux of atoms to form second nuclei after exposing the first nuclei to an inert atmosphere.
摘要翻译： 一种形成纳米团簇的方法包括提供半导体衬底; 在所述半导体衬底上形成电介质层，将所述半导体衬底暴露于所述第一原子通量，以在所述电介质层上形成第一核，在将所述半导体衬底暴露于所述第一焊剂之后，将所述第一核暴露于第一惰性气氛， 半导体衬底到第二个原子通量，以在将第一核暴露于惰性气氛之后形成第二核。
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公开(公告)号：US20060186457A1
公开(公告)日：2006-08-24
申请号：US11061005
申请日：2005-02-18
IPC分类号： H01L29/788
CPC分类号： H01L21/26586 , H01L27/115 , H01L27/11521 , H01L29/1083 , H01L29/7881
摘要： A technique to speed up the programming of a non-volatile memory device that has a floating body actively removes holes from the floating body that have accumulated after performing hot carrier injection (HCI). The steps of HCI and active hole removal can be alternated until the programming is complete. The active hole removal is faster than passively allowing holes to be removed, which can take milliseconds. The active hole removal can be achieved by reducing the drain voltage to a negative voltage and reducing the gate voltage as well. This results in directly withdrawing the holes from the floating body to the drain. Alternatively, reducing the drain voltage while maintaining current flow stops impact ionization while sub channel current collects the holes. Further alternatively, applying a negative gate voltage causes electrons generated by band to band tunneling and impact ionization near the drain to recombine with holes.
摘要翻译： 一种用于加速具有浮体的非易失性存储装置的编程的技术主动地从执行热载流子注入（HCI）之后累积的浮体中去除空穴。 HCI和有源孔去除的步骤可以交替，直到编程完成。 有源孔移除比被动地更快地允许孔被去除，这可能需要几毫秒。 有源孔去除可以通过将漏极电压降低到负电压并降低栅极电压来实现。 这导致从浮体直接排出孔到排水管。 或者，在保持电流的同时降低漏极电压停止冲击电离，而子通道电流收集孔。 或者，施加负栅极电压使得通过带状隧穿产生的电子和靠近漏极的冲击电离与空穴重新组合。
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公开(公告)号：US20060166452A1
公开(公告)日：2006-07-27
申请号：US11043826
申请日：2005-01-26
申请人： Rajesh Rao , Ramachandran Muralidhar , Bruce White
发明人： Rajesh Rao , Ramachandran Muralidhar , Bruce White
IPC分类号： H01L21/331
CPC分类号： H01L29/42348 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/518
摘要： A nanocrystal non-volatile memory (NVM) has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped.
摘要翻译： 纳米晶体非易失性存储器（NVM）在控制栅极和纳米晶体之间具有电介质，其具有足够的氮含量以减少电介质中的电子被俘获的位置。 这是通过对氮浓度进行分级而实现的。 靠近纳米晶体的氮浓度最高，其中电子/空穴阱的浓度趋于最高，并且朝向电子/空穴陷阱的浓度较低的对照栅极减小。 已经发现这具有减少电荷被捕获的位置数量的有益效果。
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公开(公告)号：US20060105522A1
公开(公告)日：2006-05-18
申请号：US10987047
申请日：2004-11-12
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/823462 , H01L27/11526 , H01L27/11546 , H01L27/11573
摘要： An integrated circuit and method of forming an integrated circuit having a memory portion minimizes an amount of oxidation of nanocluster storage elements in the memory portion. A first region of the integrated circuit has non-memory devices, each having a control electrode or gate formed of a single conductive layer of material. A second region of the integrated circuit has a plurality of memory cells, each having a control electrode of at least two conductive layers of material that are positioned one overlying another. The at least two conductive layers are at substantially a same electrical potential when operational and form a single gate electrode. In one form each memory cell gate has two polysilicon layers overlying a nanocluster storage layer.
摘要翻译： 集成电路和形成具有存储器部分的集成电路的方法使存储器部分中的纳米簇存储元件的氧化量最小化。 集成电路的第一区域具有非存储器件，每个都具有由单个导电材料层形成的控制电极或栅极。 集成电路的第二区域具有多个存储单元，每个存储单元具有至少两个彼此重叠的导电材料层的控制电极。 当操作并且形成单个栅电极时，至少两个导电层处于基本相同的电势。 在一种形式中，每个存储单元栅极具有覆盖在纳米团簇存储层上的两个多晶硅层。
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公开(公告)号：US20060046406A1
公开(公告)日：2006-03-02
申请号：US10930892
申请日：2004-08-31
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L29/1608 , H01L29/267 , H01L29/66833 , H01L29/7881
摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. This results in it being more difficult to generate electron/hole pairs by impact ionization. Thus, it can be advantageous to use the SiC region for the drain during a read. The SiGe is used as the drain for programming and erase. The SiGe, having a smaller bandgap than the silicon substrate results in improved programming by generating electron/hole pairs by impact ionization and improved erasing by generating electron hole/pairs by band-to-band tunneling, both at lower voltage levels.
摘要翻译： 非易失性存储器（NVM）具有硅锗（SiGe）漏极和硅碳（SiC）源。 作为SiC的源提供通道上的应力，其改善N沟道迁移率。 SiC也具有比衬底更大的带隙，这是硅。 这导致通过冲击电离产生电子/空穴对更困难。 因此，在读取期间使用SiC区域用于漏极是有利的。 SiGe用作编程和擦除的漏极。 具有比硅衬底更小的带隙的SiGe通过在较低电压电平下通过产生电子/空穴对的冲击电离和通过频带隧穿产生电子空穴/对来改善擦除来改善编程。
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