公开(公告)号：US20060194438A1

公开(公告)日：2006-08-31

申请号：US10876820

申请日：2004-06-25

申请人： Rajesh Rao ,  Ramachandran Muralidhar ,  Robert Steimle ,  Gowrishankar Chindalore

发明人： Rajesh Rao ,  Ramachandran Muralidhar ,  Robert Steimle ,  Gowrishankar Chindalore

IPC分类号： H01L21/302 ,  H01L31/112 ,  H01L21/36

CPC分类号： H01L27/11546 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42332

摘要： A plurality of memory cell devices is formed by using an intermediate dual polysilicon-nitride control electrode stack overlying nanoclusters. The stack includes a first-formed polysilicon-nitride layer and a second-formed polysilicon-containing layer. The second-formed polysilicon-containing layer is removed from areas containing the plurality of memory cells. In one form the second-formed polysilicon-containing layer also contains a nitride portion which is also removed, thereby leaving the first-formed polysilicon-nitride layer for the memory cell devices. In another form the second-formed ploysilicon-containing layer does not contain nitride and a nitride portion of the first-formed polysilicon-nitride layer is also removed. In the latter form a subsequent nitride layer is formed over the remaining polysilicon layer. In both forms a top portion of the device is protected from oxidation, thereby preserving size and quality of underlying nanoclusters. Gate electrodes of devices peripheral to the memory cell devices also use the second-formed polysilicon-containing layer.

摘要翻译： 通过使用覆盖纳米团簇的中间双重多晶氮化物控制电极堆叠形成多个存储单元器件。 堆叠包括第一形成的多晶氮化物层和第二形成的含多晶硅的层。 第二形成的含多晶硅的层从包含多个存储单元的区域中去除。 在一种形式中，第二形成的含多晶硅的层还包含也被去除的氮化物部分，从而留下用于存储单元器件的第一形成的多晶氮化物层。 在另一种形式中，第二形成的含硅层不含有氮化物，并且还去除了第一形成的多晶氮化物层的氮化物部分。 在后一种形式中，在剩余的多晶硅层上形成随后的氮化物层。 在这两种形式中，器件的顶部部分被保护免受氧化，从而保持下面的纳米簇的尺寸和质量。 存储单元器件外围的器件的栅电极也使用第二形成的含多晶硅的层。

公开(公告)号：US20050059213A1

公开(公告)日：2005-03-17

申请号：US10663621

申请日：2003-09-16

申请人： Robert Steimle ,  Ramachandran Muralidhar ,  Wayne Paulson ,  Rajesh Rao ,  Bruce White ,  Erwin Prinz

发明人： Robert Steimle ,  Ramachandran Muralidhar ,  Wayne Paulson ,  Rajesh Rao ,  Bruce White ,  Erwin Prinz

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/115 ,  H01L29/423

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42332

摘要： A process of forming a device with nanoclusters. The process includes forming nanoclusters (e.g. silicon nanocrystals) and forming an oxidation barrier layer over the nanoclusters to inhibit oxidizing agents from oxidizing the nanoclusters during a subsequent formation of a dielectric of the device. At least a portion of the oxidation barrier layer is removed after the formation of the dielectric. In one example, the device is a memory wherein the nanoclusters are utilized as charge storage locations for charge storage transistors of the memory. In this example, the oxidation barrier layer protects the nanoclusters from oxidizing agents due to the formation of gate dielectric for high voltage transistors of the memory.

公开(公告)号：US20060030105A1

公开(公告)日：2006-02-09

申请号：US10912825

申请日：2004-08-06

申请人： Erwin Prinz ,  Ramachandran Muralidhar ,  Rajesh Rao ,  Michael Sadd ,  Robert Steimle ,  Craig Swift ,  Bruce White

发明人： Erwin Prinz ,  Ramachandran Muralidhar ,  Rajesh Rao ,  Michael Sadd ,  Robert Steimle ,  Craig Swift ,  Bruce White

IPC分类号： H01L21/336

CPC分类号： B82Y10/00 ,  G11C16/0475 ,  G11C16/14 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332

摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.

摘要翻译： 在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电 场到纳米团簇放电半导体器件。 施加紫外线（UV）光时可能会发生电场。 在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

公开(公告)号：US20060211199A1

公开(公告)日：2006-09-21

申请号：US11082094

申请日：2005-03-16

申请人： Rajesh Rao ,  Ramachandran Muralidhar ,  Robert Steimle

发明人： Rajesh Rao ,  Ramachandran Muralidhar ,  Robert Steimle

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/42332 ,  H01L29/66825

摘要： A method for removing nanoclusters from a semiconductor device includes etching a selected portion of an insulating layer, flowing a reducing gas over the semiconductor device at a temperature in a range of 400-900 degrees Celsius, and flowing a gas comprising halogen over the semiconductor device a temperature in a range of 400-900 degrees Celsius. In another form, a method for removing the nanoclusters includes implanting germanium or nitrogen into the nanoclusters, etching a selected portion of the insulating layer using a dry etch process, and removing the layer of nanoclusters using a wet etch process that is selective to an insulating layer.

摘要翻译： 一种用于从半导体器件中去除纳米团簇的方法包括：在400-900摄氏度的温度范围内蚀刻绝缘层的选定部分，使还原气体在半导体器件上流动，并使包含卤素的气体流过半导体器件 温度在400-900摄氏度的范围内。 在另一种形式中，用于去除纳米团簇的方法包括将锗或氮注入到纳米团簇中，使用干蚀刻工艺蚀刻绝缘层的选定部分，以及使用对绝缘选择性的湿蚀刻工艺去除纳米团簇层 层。

公开(公告)号：US20050041503A1

公开(公告)日：2005-02-24

申请号：US10950855

申请日：2004-09-27

申请人： Gowrishankar Chindalore ,  Rajesh Rao ,  Jane Yater

发明人： Gowrishankar Chindalore ,  Rajesh Rao ,  Jane Yater

IPC分类号： G11C5/00 ,  G11C16/28 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/76

CPC分类号： H01L27/11568 ,  B82Y10/00 ,  G11C16/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11573

摘要： A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46). The read control circuit (42) senses a drain current of the reference transistor (46) and adjusts the gate bias voltage to maintain the reference current at a substantially constant value relative to the cell current.

摘要翻译： 非易失性存储器（30）包括纳米晶体存储单元（50,51,53）。 存储单元晶体管（50,51,53）的编程和擦除阈值电压作为编程/擦除操作的次数增加。 在读取操作期间，参考晶体管（46）提供用于与单元电流进行比较的参考电流。 除了参考晶体管（46）不包括纳米晶体之外，参考晶体管（46）由与制造存储单元晶体管（50,51,53）类似的工艺制成。 通过使用类似的工艺来使参考晶体管（46）和存储单元晶体管（50,51,53）同时工作，参考晶体管（46）的阈值电压将跟踪存储单元晶体管（50）的阈值电压偏移 ，51,53）。 提供读控制电路（42）以偏置参考晶体管（46）的栅极。 读取控制电路（42）感测参考晶体管（46）的漏极电流并调整栅极偏置电压，以使参考电流相对于单元电流保持在基本恒定的值。

公开(公告)号：US20050007820A1

公开(公告)日：2005-01-13

申请号：US10609359

申请日：2003-06-27

申请人： Gowrishankar Chindalore ,  Rajesh Rao ,  Jane Yater

发明人： Gowrishankar Chindalore ,  Rajesh Rao ,  Jane Yater

IPC分类号： G11C20060101 ,  G11C11/34 ,  G11C16/00 ,  G11C16/06 ,  G11C16/28 ,  H01L21/28 ,  H01L21/8247

CPC分类号： B82Y10/00 ,  G11C16/28 ,  G11C2216/06 ,  H01L21/28273 ,  H01L27/11531

摘要： A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46). The read control circuit (42) senses a drain current of the reference transistor (46) and adjusts the gate bias voltage to maintain the reference current at a substantially constant value relative to the cell current.

摘要翻译： 非易失性存储器（30）包括纳米晶体存储单元（50,51,53）。 存储单元晶体管（50,51,53）的编程和擦除阈值电压作为编程/擦除操作的次数增加。 在读取操作期间，参考晶体管（46）提供用于与单元电流进行比较的参考电流。 除了参考晶体管（46）不包括纳米晶体之外，参考晶体管（46）由与制造存储单元晶体管（50,51,53）类似的工艺制成。 通过使用类似的工艺来使参考晶体管（46）和存储单元晶体管（50,51,53）同时工作，参考晶体管（46）的阈值电压将跟踪存储单元晶体管（50）的阈值电压偏移 ，51,53）。 提供读控制电路（42）以偏置参考晶体管（46）的栅极。 读取控制电路（42）感测参考晶体管（46）的漏极电流并调整栅极偏置电压，以使参考电流相对于单元电流保持在基本恒定的值。

公开(公告)号：US07479429B2

公开(公告)日：2009-01-20

申请号：US11669307

申请日：2007-01-31

申请人： Rajesh Rao ,  Ramachandran Muralidhar ,  Leo Mathew

发明人： Rajesh Rao ,  Ramachandran Muralidhar ,  Leo Mathew

IPC分类号： H01L21/336

CPC分类号： H01L29/7923 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/7887

摘要： A multi-bit split-gate memory device is formed over a substrate. A storage layer is formed over the substrate. A first conductive layer is formed over the storage layer. A thickness of a portion of the conductive layer is removed to leave a pillar of the conductive layer and an area of reduced thickness of the conductive layer. A first sidewall spacer is formed adjacent to the pillar to cover a first portion and a second portion of the area of reduced thickness of the conductive layer. The pillar is replaced with a select gate. The area of reduced thickness is selectively removed to leave the first and second portions as control gates.

摘要翻译： 在衬底上形成多位分离栅极存储器件。 在衬底上形成存储层。 在存储层上形成第一导电层。 去除导电层的一部分的厚度以留下导电层的柱和导电层的厚度减小的面积。 形成邻近柱的第一侧壁间隔物以覆盖导电层厚度减小区域的第一部分和第二部分。 柱子被一个选择门取代。 选择性地去除厚度减小的区域以留下第一和第二部分作为控制门。

公开(公告)号：US20060199335A1

公开(公告)日：2006-09-07

申请号：US11071977

申请日：2005-03-04

申请人： Rajesh Rao ,  Ramachandran Muralidhar

发明人： Rajesh Rao ,  Ramachandran Muralidhar

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66772

摘要： An electronic device can include an NVM structure and a gate electrode outside an NVM array. In one embodiment, a first gate dielectric layer and a first gate electrode layer are formed before forming NVM cells within an NVM array. The first gate electrode layer helps to protect the first gate dielectric layer from becoming thinner or thicker during subsequent processing used to form NVM cells. In another embodiment, NVM structures and transistor structures can be formed where the NVM structures have one more spacer adjacent to the NVM structures as compared to the transistor structures.

摘要翻译： 电子设备可以包括NVM结构和NVM阵列外部的栅电极。 在一个实施例中，在形成NVM阵列内的NVM单元之前形成第一栅极介电层和第一栅极电极层。 第一栅极电极层有助于在用于形成NVM电池的后续处理期间保护第一栅极介电层变得更薄或更厚。 在另一个实施例中，可以形成NVM结构和晶体管结构，其中与晶体管结构相比，NVM结构具有与NVM结构相邻的更多间隔区。

公开(公告)号：US07557008B2

公开(公告)日：2009-07-07

申请号：US11625882

申请日：2007-01-23

申请人： Rajesh Rao ,  Ramachandran Muralidhar

发明人： Rajesh Rao ,  Ramachandran Muralidhar

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

摘要： A method forms a nonvolatile memory device using a semiconductor substrate. A charge storage layer is formed overlying the semiconductor substrate and a layer of gate material is formed overlying the charge storage layer to form a control gate electrode. A protective layer overlies the layer of gate material. Dopants are implanted into the semiconductor substrate and are self-aligned to the control gate electrode on at least one side of the control gate electrode to form a source and a drain in the semiconductor substrate on opposing sides of the control gate electrode. The protective layer prevents the dopants from penetrating into the control gate electrode. The protective layer that overlies the layer of gate material is removed. Electrical contact is made to the control gate electrode, the source and the drain. In one form a select gate is also provided in the memory device.

摘要翻译： 一种方法形成使用半导体衬底的非易失性存储器件。 形成覆盖在半导体衬底上的电荷存储层，并且形成覆盖电荷存储层的栅极材料层以形成控制栅电极。 保护层覆盖栅极材料层。 将掺杂剂注入到半导体衬底中，并且在控制栅电极的至少一侧上与控制栅电极自对准，以在控制栅电极的相对侧上的半导体衬底中形成源极和漏极。 保护层防止掺杂剂渗入控制栅电极。 覆盖栅极材料层的保护层被去除。 与控制栅电极，源极和漏极电接触。 在一种形式中，选择栅极也被提供在存储器件中。

公开(公告)号：US20080176371A1

公开(公告)日：2008-07-24

申请号：US11625882

申请日：2007-01-23

申请人： Rajesh Rao ,  Ramachandran Muralidhar

发明人： Rajesh Rao ,  Ramachandran Muralidhar

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

摘要： A method forms a nonvolatile memory device using a semiconductor substrate. A charge storage layer is formed overlying the semiconductor substrate and a layer of gate material is formed overlying the charge storage layer to form a control gate electrode. A protective layer overlies the layer of gate material. Dopants are implanted into the semiconductor substrate and are self-aligned to the control gate electrode on at least one side of the control gate electrode to form a source and a drain in the semiconductor substrate on opposing sides of the control gate electrode. The protective layer prevents the dopants from penetrating into the control gate electrode. The protective layer that overlies the layer of gate material is removed. Electrical contact is made to the control gate electrode, the source and the drain. In one form a select gate is also provided in the memory device.

摘要翻译： 一种方法形成使用半导体衬底的非易失性存储器件。 形成覆盖在半导体衬底上的电荷存储层，并且形成覆盖电荷存储层的栅极材料层以形成控制栅电极。 保护层覆盖栅极材料层。 将掺杂剂注入到半导体衬底中，并且在控制栅电极的至少一侧上与控制栅电极自对准，以在控制栅电极的相对侧上的半导体衬底中形成源极和漏极。 保护层防止掺杂剂渗入控制栅电极。 覆盖栅极材料层的保护层被去除。 与控制栅电极，源极和漏极电接触。 在一种形式中，选择栅极也被提供在存储器件中。