公开(公告)号：US20100022073A1

公开(公告)日：2010-01-28

申请号：US12573589

申请日：2009-10-05

申请人： Eugene A. Fitzgerald ,  Nichole Gerrish

发明人： Eugene A. Fitzgerald ,  Nichole Gerrish

IPC分类号： H01L21/20

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054

摘要： A method of fabricating a circuit comprising an nMOSFET includes providing a substrate, depositing a strain-inducing material comprising germanium over the substrate, and integrating a pMOSFET on the substrate, the pMOSFET comprising a strained channel having a surface roughness of less than 1 nm. The strain-inducing material is proximate to and in contact with the pMOSFET channel, the strain in the pMOSFET channel is induced by the strain-inducing material, and a source and a drain of the pMOSFET are at least partially formed in the strain-inducing material.

摘要翻译： 制造包括nMOSFET的电路的方法包括提供衬底，在衬底上沉积包含锗的应变诱导材料，以及在衬底上集成pMOSFET，pMOSFET包括表面粗糙度小于1nm的应变通道。 应变诱导材料接近并与pMOSFET通道接触，pMOSFET通道中的应变由应变诱导材料诱导，并且pMOSFET的源极和漏极在应变诱导中至少部分地形成 材料。

公开(公告)号：US07420201B2

公开(公告)日：2008-09-02

申请号：US11125507

申请日：2005-05-10

申请人： Thomas A. Langdo ,  Matthew T. Currie ,  Richard Hammond ,  Anthony J. Lochtefeld ,  Eugene A. Fitzgerald

发明人： Thomas A. Langdo ,  Matthew T. Currie ,  Richard Hammond ,  Anthony J. Lochtefeld ,  Eugene A. Fitzgerald

IPC分类号： H01L21/336

CPC分类号： H01L29/7847 ,  H01L21/28518 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66242 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/66916 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78687

摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

摘要翻译： 应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

公开(公告)号：US07414259B2

公开(公告)日：2008-08-19

申请号：US11126550

申请日：2005-05-11

申请人： Thomas A. Langdo ,  Matthew T. Currie ,  Richard Hammond ,  Anthony J. Lochtefeld ,  Eugene A. Fitzgerald

发明人： Thomas A. Langdo ,  Matthew T. Currie ,  Richard Hammond ,  Anthony J. Lochtefeld ,  Eugene A. Fitzgerald

IPC分类号： H01L31/0392

CPC分类号： H01L29/7847 ,  H01L21/28518 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66242 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/66916 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78687

摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

摘要翻译： 应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

公开(公告)号：US07390701B2

公开(公告)日：2008-06-24

申请号：US11087781

申请日：2005-03-23

申请人： Zhiyuan Cheng ,  Eugene A. Fitzgerald ,  Dimitri Antoniadis

发明人： Zhiyuan Cheng ,  Eugene A. Fitzgerald ,  Dimitri Antoniadis

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/78687

摘要： A multiple-gate FET structure includes a semiconductor substrate. A gate region is formed on the semiconductor substrate. The gate region comprises a gate portion and a channel portion. The gate portion has at least two opposite vertical surfaces adjacent to the channel portion. A source region abuts the gate region at one end, and a drain diffusion region abuts the gate region at the other end.

摘要翻译： 多栅极FET结构包括半导体衬底。 在半导体衬底上形成栅区。 栅极区域包括栅极部分和沟道部分。 栅极部分具有与通道部分相邻的至少两个相对的垂直表面。 源极区域在一端邻接栅极区域，漏极扩散区域在另一端邻接栅极区域。

公开(公告)号：US07259388B2

公开(公告)日：2007-08-21

申请号：US11120675

申请日：2005-05-03

申请人： Thomas A. Langdo ,  Matthew T. Currie ,  Richard Hammond ,  Anthony J. Lochtefeld ,  Eugene A. Fitzgerald

发明人： Thomas A. Langdo ,  Matthew T. Currie ,  Richard Hammond ,  Anthony J. Lochtefeld ,  Eugene A. Fitzgerald

IPC分类号： H01L31/039

CPC分类号： H01L29/7847 ,  H01L21/28518 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/76259 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66242 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/66916 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78687

摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

摘要翻译： 应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

公开(公告)号：US07250359B2

公开(公告)日：2007-07-31

申请号：US10022689

申请日：2001-12-17

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L21/20

CPC分类号： H01L21/02505 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  Y10S438/933

摘要： A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.

摘要翻译： 一种半导体结构，包括半导体衬底，在衬底上的至少一个第一晶体外延层，第一层具有被平坦化的表面，以及在至少一个第一层上的至少一个第二晶体外延层。 在本发明的另一个实施例中，提供了包括硅衬底和在硅衬底上生长的GeSi分级区域的半导体结构，压缩应变被并入渐变区域以抵消在热处理期间结合的拉伸应变。 在本发明的另一个实施例中，提供了一种半导体结构，其包括半导体衬底，具有在衬底上生长的渐变区域的第一层，压缩应变结合在渐变区域中以抵消在热处理期间结合的拉伸应变， 所述第一层具有平坦化的表面，以及设置在所述第一层上的第二层。 在本发明的另一个实施例中，提供了一种制造半导体结构的方法，包括提供半导体衬底，在衬底上提供至少一个第一晶体外延层，并平坦化第一层的表面。

公开(公告)号：US07217668B2

公开(公告)日：2007-05-15

申请号：US11013838

申请日：2004-12-16

申请人： Eugene A. Fitzgerald ,  Richard Hammond ,  Matthew Currie

发明人： Eugene A. Fitzgerald ,  Richard Hammond ,  Matthew Currie

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L21/336

CPC分类号： H01L29/66477 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/28238 ,  H01L29/1054 ,  H01L29/78 ,  H01L29/7838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.

摘要翻译： 一种制造半导体器件的方法，包括提供半导体异质结构，所述异质结构在衬底上具有松弛的Si 1-x Ge 2 x层，在弛豫时产生应变通道层 Si 1-x Ge Ge层，以及Si 1-y Ge Ge层; 除去Si 1-y Y y Y y层; 并提供介电层。 电介质层包括MISFET的栅极电介质。 在替代实施例中，异质结构包括SiGe间隔层和Si层。

公开(公告)号：US07081410B2

公开(公告)日：2006-07-25

申请号：US10826156

申请日：2004-04-16

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L21/302

CPC分类号： H01L21/02505 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  Y10S438/933

摘要： A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer. In still another embodiment of the invention there is provided a method of fabricating a semiconductor structure including providing a semiconductor substrate, providing at least one first crystalline epitaxial layer on the substrate, and planarizing the surface of the first layer.

公开(公告)号：US07074623B2

公开(公告)日：2006-07-11

申请号：US10456708

申请日：2003-06-06

申请人： Anthony J. Lochtefeld ,  Thomas A. Langdo ,  Richard Hammond ,  Matthew T. Currie ,  Glyn Braithwaite ,  Eugene A. Fitzgerald

发明人： Anthony J. Lochtefeld ,  Thomas A. Langdo ,  Richard Hammond ,  Matthew T. Currie ,  Glyn Braithwaite ,  Eugene A. Fitzgerald

IPC分类号： H01L21/335 ,  H01L21/00 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/76254 ,  H01L21/76259 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66916 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78687

摘要： The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

摘要翻译： 应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

公开(公告)号：US06974735B2

公开(公告)日：2005-12-13

申请号：US10216085

申请日：2002-08-09

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L21/8238 ,  H01L29/10 ,  H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/1054 ,  Y10S438/933

摘要： A semiconductor-based device includes a channel layer, which includes a distal layer and a proximal layer in contact with the distal layer. The distal layer supports at least a portion of hole conduction for at least one p-channel component, and the proximal layer supports at least a portion of electron conduction for at least one n-channel component. The proximal layer has a thickness that permits a hole wave function to effectively extend from the proximal layer into the distal layer to facilitate hole conduction by the distal layer. A method for fabricating a semiconductor-based device includes providing a distal portion of a channel layer and providing a proximal portion of the channel layer.

摘要翻译： 基于半导体的器件包括沟道层，其包括远端层和与远端层接触的近端层。 远端层支撑至少一个p沟道分量的至少一部分空穴传导，并且近端支撑至少一个n沟道分量的至少一部分电子传导。 近端层具有允许空穴波函数从近端层有效地延伸到远侧层中的厚度，以便于远端层的空穴传导。 一种用于制造基于半导体的器件的方法包括提供沟道层的远端部分并提供沟道层的近端部分。