公开(公告)号：US20210057271A1

公开(公告)日：2021-02-25

申请号：US16547474

申请日：2019-08-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ryan W. Sporer ,  Jiehui Shu

IPC: H01L21/762 ,  H01L21/74 ,  H01L21/768 ,  H01L29/06

Abstract: A method forms a trench isolation opening extending into an SOI substrate, and forms an etch stop member in a portion of the insulator layer abutting a side of the trench isolation opening. The etch stop member has a higher etch selectivity than the insulator layer of the SOI substrate. A trench isolation is formed in the trench isolation opening. A contact is formed to a portion of the semiconductor layer of the SOI substrate. The etch stop member is structured to prevent contact punch through to the base substrate of the SOI substrate.

公开(公告)号：US20210005601A1

公开(公告)日：2021-01-07

申请号：US16942816

申请日：2020-07-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Bharat V. Krishnan

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

Abstract: Disclosed are a method of forming a fin-type field effect transistor (FINFET) and a FINFET structure. In the method, isolation regions are formed on opposing sides of a semiconductor fin. Each isolation region is shorter than the fin, has a lower isolation portion adjacent to a lower fin portion, and has an upper isolation portion that is narrower than the lower isolation portion and separated from a bottom section of an upper fin portion by a space. Surface oxidation of the upper fin portion thins the top section, but leaves the bottom section relatively wide. During gate formation, the gate dielectric layer fills the spaces between the bottom section of the upper fin portion and the adjacent isolation regions. Thus, the gate conductor layer is formed above any fin bulge area and degradation of gate control over the channel region due to a non-uniform fin width is minimized or avoided.

公开(公告)号：US20200335435A1

公开(公告)日：2020-10-22

申请号：US16918053

申请日：2020-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/525

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.

公开(公告)号：US20200312947A1

公开(公告)日：2020-10-01

申请号：US16369788

申请日：2019-03-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang

IPC: H01L49/02 ,  H01L29/78 ,  H01L27/088 ,  H01L21/768 ,  H01L21/762 ,  H01L23/522

Abstract: Embodiments of the disclosure provide a resistor structure for an integrated circuit (IC) and related methods. The resistor structure may include: a shallow trench isolation (STI) region on a substrate; a resistive material above a portion of the shallow trench isolation (STI) region; a gate structure on another portion of the STI region, above the substrate, and horizontally displaced from the resistive material; an insulative barrier above the STI region and contacting an upper surface and sidewalls of the resistive material, an upper surface of the insulative barrier being substantially coplanar with an upper surface of the gate structure; and a pair of contacts within the insulative barrier, and each positioned on an upper surface of the resistive material

公开(公告)号：US20200243643A1

公开(公告)日：2020-07-30

申请号：US16256252

申请日：2019-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Jiehui Shu ,  Hui Zang

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative integrated circuit product disclosed herein includes a single diffusion break (SDB) isolation structure positioned between a first fin portion and a second fin portion, wherein the first fin portion comprises a first end surface and the second fin portion comprises a second end surface. In this example, the SDB structure includes a conformal liner layer that engages the first end surface of the first fin portion and the second end surface of the second fin portion, an insulating material positioned on the conformal liner layer, a cap structure positioned above an upper surface of the insulating material and an air gap positioned between a bottom surface of the cap structure and the upper surface of the insulating material.

公开(公告)号：US10699957B2

公开(公告)日：2020-06-30

申请号：US16201449

申请日：2018-11-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Jiehui Shu ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L29/423 ,  H01L27/088 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3105

Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.

公开(公告)号：US10685840B2

公开(公告)日：2020-06-16

申请号：US16193960

申请日：2018-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang

IPC: H01L29/76 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78 ,  H01L27/088 ,  H01L21/28 ,  H01L23/535 ,  H01L29/49 ,  H01L29/66

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a plurality of gate structures comprising a gate cap, sidewall spacers and source and drain regions; source and drain metallization features extending to the source and drain regions; and a liner extending along an upper portion of the sidewall spacers of at least one of the plurality of gate structures.

公开(公告)号：US20200168509A1

公开(公告)日：2020-05-28

申请号：US16201449

申请日：2018-11-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Ruilong Xie ,  Jiehui Shu ,  Chanro Park ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/033 ,  H01L29/423 ,  H01L27/088

Abstract: Methods of forming a structure that includes field-effect transistor and structures that include a field effect-transistor. A dielectric cap is formed over a gate structure of a field-effect transistor, and an opening is patterned that extends fully through the dielectric cap to divide the dielectric cap into a first section and a second section spaced across the opening from the first surface. First and second dielectric spacers are respectively selectively deposited on respective first and second surfaces of the first and second sections of the dielectric cap to shorten the opening. A portion of the gate structure exposed through the opening between the first and second dielectric spacers is etched to form a cut that divides the gate electrode into first and second sections disconnected by the cut. A dielectric material is deposited in the opening and in the cut to form a dielectric pillar.

公开(公告)号：US10566202B1

公开(公告)日：2020-02-18

申请号：US16203623

申请日：2018-11-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang ,  Hong Yu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423

Abstract: A method of fabricating a semiconductor device is provided, including providing sacrificial gate structures over a plurality of fins. The sacrificial gate structures include a sacrificial first gate structure and a sacrificial second gate structure. A first gate cut process is performed to form a first gate cut opening in the sacrificial first gate structure, and a second gate cut opening in the sacrificial second gate structure. A first dielectric layer is deposited in the first gate cut opening and the second gate cut opening. The first dielectric layer completely fills the first gate cut opening and partially fills the second gate cut opening. The first dielectric layer is removed from the second gate cut opening, and a second gate cut process is performed. A second dielectric layer is deposited in the second gate cut opening to form a gate cut structure.

公开(公告)号：US20200052106A1

公开(公告)日：2020-02-13

申请号：US16101162

申请日：2018-08-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Neal Makela ,  Pei Liu ,  Jiehui Shu ,  Chih-chiang Chang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/28

Abstract: At least one method, apparatus, and system providing semiconductor devices comprising a first gate having a first width and comprising a first work function metal (WFM); a first liner disposed over the first WFM; a first gate metal having a first height; and a first pinch-off spacer over the first WFM, the first liner, and the first gate metal to above the first height; and a second gate having a second width greater than the first width, and comprising a second WFM; a second liner disposed over the second WFM; a second gate metal having substantially the first height; and a first conformal spacer over the second WFM and the second liner.