公开(公告)号：US09634088B1

公开(公告)日：2017-04-25

申请号：US15185267

申请日：2016-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Juergen Thees ,  Peter Baars

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0642 ,  H01L29/16 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78684

Abstract: A method of forming a semiconductor device is disclosed including providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, and forming a transistor device on the silicon-on-insulator substrate including providing a gate structure on the semiconductor layer having a gate electrode and a first cap layer on the gate electrode, growing an oxide liner on the transistor device having a first part covering the gate structure and a second part covering the semiconductor layer, forming a second cap layer on the oxide liner, at least partially removing the second part of the oxide liner underneath the second cap layer and the first part of the oxide liner, and epitaxially forming raised source/drain regions on the semiconductor layer.

公开(公告)号：US09553046B2

公开(公告)日：2017-01-24

申请号：US14718502

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L21/331 ,  H01L23/525 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L23/5256 ,  H01L21/84 ,  H01L27/1203

Abstract: A method of forming a semiconductor device comprising a fuse is provided including providing a semiconductor-on-insulator (SOI) structure comprising an insulating layer and a semiconductor layer formed on the insulating layer, forming raised semiconductor regions on the semiconductor layer adjacent to a central portion of the semiconductor layer and performing a silicidation process of the central portion of the semiconductor layer and the raised semiconductor regions to form a silicided semiconductor layer and silicided raised semiconductor regions.

Abstract translation: 提供一种形成包括熔丝的半导体器件的方法，包括：提供绝缘层上的绝缘体上半导体结构（SOI）结构和形成在绝缘层上的半导体层，在与中心相邻的半导体层上形成凸起的半导体区域 并且对半导体层的中心部分和凸起的半导体区域进行硅化处理，以形成硅化半导体层和硅化凸起的半导体区域。

公开(公告)号：US09502564B2

公开(公告)日：2016-11-22

申请号：US15164374

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78639 ,  H01L29/78654

Abstract: A semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and a buried insulating material region disposed in the active region under the gate structure. The buried insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth of the active region. The source/drain regions have a depth greater than a top surface of the buried insulating material region.

Abstract translation: 半导体器件包括形成在半导体衬底中的有源区，设置在有源区上的栅极结构，形成在与栅结构对准的有源区中的源极/漏极区，以及设置在有源区内的掩埋绝缘材料区 门结构。 掩埋绝缘材料区域被有源区域包围，并且沿着有源区域的深度与栅极结构下方的有源区域中的沟道区域相邻。 源/漏区具有大于掩埋绝缘材料区的顶表面的深度。

公开(公告)号：US20160315016A1

公开(公告)日：2016-10-27

申请号：US14695232

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/76264 ,  H01L21/84 ,  H01L21/845 ,  H01L27/127 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/78684

Abstract: A method of forming a semiconductor device is provided including providing a semiconductor-on-insulator (SOI) wafer comprising a first semiconductor layer comprising a first material component and formed on a buried oxide (BOX) layer, and forming a channel region of a P-channel transistor device, including forming a second semiconductor layer only over a first portion of the first semiconductor layer, wherein the second semiconductor layer comprises the first material component and a second material component different from the first material component, forming an opening in the first semiconductor layer outside the first portion and subsequently performing a thermal anneal to push the second material component from the second semiconductor layer into the first semiconductor layer.

Abstract translation: 提供一种形成半导体器件的方法，包括：提供绝缘体上半导体（SOI）晶片，其包括第一半导体层，其包含第一材料成分并形成在掩埋氧化物（BOX）层上，并形成P 通道晶体管器件，包括只在第一半导体层的第一部分上形成第二半导体层，其中第二半导体层包括第一材料成分和与第一材料成分不同的第二材料成分，在第一 半导体层，然后进行热退火，以将第二材料成分从第二半导体层推入第一半导体层。

公开(公告)号：US20160268431A1

公开(公告)日：2016-09-15

申请号：US15164374

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78639 ,  H01L29/78654

Abstract: A semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and a buried insulating material region disposed in the active region under the gate structure. The buried insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth of the active region. The source/drain regions have a depth greater than a top surface of the buried insulating material region.

Abstract translation: 半导体器件包括形成在半导体衬底中的有源区，设置在有源区上的栅极结构，形成在与栅结构对准的有源区中的源极/漏极区，以及设置在有源区内的掩埋绝缘材料区 门结构。 掩埋绝缘材料区域被有源区域包围，并且沿着有源区域的深度与栅极结构下方的有源区域中的沟道区域相邻。 源/漏区具有大于掩埋绝缘材料区的顶表面的深度。

公开(公告)号：US20160204128A1

公开(公告)日：2016-07-14

申请号：US14592069

申请日：2015-01-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Peter Moll ,  Jan Hoentschel

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/321 ,  H01L29/66 ,  H01L27/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L49/02 ,  H01L21/84 ,  H01L21/308

CPC classification number: H01L27/1207 ,  H01L21/308 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7838

Abstract: A method of forming a semiconductor device structure includes providing a substrate with a semiconductor-on-insulator (SOI) configuration, the SOI substrate comprising a semiconductor layer formed on a buried oxide (BOX) layer which is disposed on a semiconductor bulk substrate, forming trench isolation structures delineating a first region and a second region within the SOI substrate, removing the semiconductor layer and the BOX layer in the first region for exposing the semiconductor bulk substrate within the first region, forming a first semiconductor device with an electrode in and over the exposed semiconductor bulk substrate in the first region, forming a second semiconductor device in the second region, the second semiconductor device comprising a gate structure disposed over the semiconductor layer and the BOX layer in the second region, and performing a polishing process for defining a common height level to which the electrode and the gate structure substantially extend.

Abstract translation: 一种形成半导体器件结构的方法包括：提供具有绝缘体上半导体（SOI）结构的衬底，所述SOI衬底包括形成在半导体本体衬底上的掩埋氧化物（BOX）层上形成的半导体层，形成 描绘SOI衬底内的第一区域和第二区域的沟槽隔离结构，去除第一区域中的半导体层和BOX层，用于在第一区域内暴露半导体本体衬底，形成具有电极的第一半导体器件 在所述第一区域中暴露的半导体体基板，在所述第二区域中形成第二半导体器件，所述第二半导体器件包括设置在所述半导体层上的栅极结构和所述第二区域中的BOX层，以及执行用于定义 电极和栅极结构基本上延伸的公共高度电平。

公开(公告)号：US20160118499A1

公开(公告)日：2016-04-28

申请号：US14521939

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78639 ,  H01L29/78654

Abstract: The present disclosure provides in some aspects a semiconductor device and a method of forming a semiconductor device. According to some illustrative embodiments herein, the semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and an insulating material region buried into the active region under the gate structure, wherein the insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth direction of the active region.

Abstract translation: 本公开在一些方面提供半导体器件和形成半导体器件的方法。 根据这里的一些说明性实施例，半导体器件包括形成在半导体衬底中的有源区，设置在有源区上的栅极结构，形成在与栅极结构对准的有源区中的源/漏区，以及绝缘材料区 埋入栅极结构下的有源区，其中绝缘材料区域被有源区域包围，并且沿着有源区域的深度方向与栅极结构下方的有源区域中的沟道区域相邻。

公开(公告)号：US20150357433A1

公开(公告)日：2015-12-10

申请号：US14299829

申请日：2014-06-09

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Hans-Peter Moll ,  Peter Baars

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/266

CPC classification number: H01L29/66545 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/78

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an implant mask overlying a dummy gate, where the implant mask produces a masked dummy gate and an exposed dummy gate. Ions are implanted into the exposed dummy gate, and the implant mask is removed. The masked dummy gate is etched with an etchant selective to the masked dummy gate over the exposed dummy gate to form a trench, and the trench is filled with a conductive material.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括形成覆盖在虚拟栅极上的注入掩模，其中所述注入掩模产生掩蔽的伪栅极和暴露的伪栅极。 将离子注入暴露的虚拟栅极中，并移除植入物掩模。 用掩蔽的伪栅极对暴露的伪栅极选择性地蚀刻掩蔽的虚拟栅极以形成沟槽，并且沟槽填充有导电材料。

公开(公告)号：US20140154854A1

公开(公告)日：2014-06-05

申请号：US14027837

申请日：2013-09-16

Applicant: Globalfoundries, Inc.

Inventor： Andy Wei ,  Peter Baars ,  Erik P. Geiss

IPC: H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

Abstract translation: 提供了用于制造集成电路的方法。 一种方法包括将多个沟槽蚀刻成硅衬底并用绝缘材料填充沟槽以描绘多个间隔开的硅片。 外延生长一层未掺杂的硅以形成翅片的上部未掺杂区域。 虚拟门结构形成为覆盖并横向于多个翅片，并且后填充材料填充在虚拟栅极结构之间。 去除虚拟栅极结构以暴露一部分散热片，并且将高k电介质材料和确定栅极电极材料的功函数沉积在鳍片的该部分上。 去除后填充材料以暴露第二部分，并且在第二部分上形成金属硅化物接触。 然后，将导电触点形成到功函数确定材料和金属硅化物。

公开(公告)号：US08716126B2

公开(公告)日：2014-05-06

申请号：US13769446

申请日：2013-02-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thomas Werner ,  Peter Baars ,  Frank Feustel

IPC: H01L21/4763

CPC classification number: H01L23/5384 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material.

Abstract translation: 本文公开了一种说明性的半导体器件，其包括具有漏极和源极区域以及栅电极结构的晶体管。 所公开的半导体器件还包括形成在第一电介质材料中的接触杆，所述接触杆连接到漏极和源极区域之一并且包括第一导电材料，所述接触棒沿晶体管的宽度方向延伸。 此外，说明性器件还包括形成在第二电介质材料中的导电线，该导电线包括具有沿晶体管的长度方向延伸的顶部宽度的上部，以及具有底部宽度延伸的下部 沿着所述长度方向小于所述上部的顶部宽度，其中所述导电线连接到所述接触杆并包括与所述第一导电材料不同的第二导电材料。