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71.发明授权Symmetric, voltage-controlled CMOS delay cell with closed-loop replica bias 失效具有闭环复制偏置的对称，压控CMOS延迟单元公开(公告)号：US06377103B1
公开(公告)日：2002-04-23
申请号：US09605459
申请日：2000-06-28
IPC分类号： H03H1126
CPC分类号： H03K5/13 , H03K2005/00026 , H03K2005/00136
摘要： A voltage-controlled CMOS delay cell includes a pair of inverters and a pair of load cells. The load cells are controllable by independent N and P bias control voltages to vary the delay of the delay cell. Symmetric P and N load capacitors in the delay cells, together with the N and P bias control voltages, provide effective rejection of noise on the power supply rails and enable the delay cell to generate symmetric low-going and high-going delays. The P bias control voltage is generated from the N bias control voltage by a closed-loop voltage control circuit. Also described are a voltage-controlled load cell, an integrated circuit, an electronic system, and a data processing system that incorporate one or more of the symmetric CMOS voltage-controlled delay cells.
摘要翻译： 压控CMOS延迟单元包括一对反相器和一对称重传感器。 负载传感器可以通过独立的N和P偏置控制电压来控制，以改变延迟单元的延迟。 延迟单元中的对称P和N负载电容以及N和P偏置控制电压可以有效地抑制电源轨上的噪声，并使延迟单元产生对称的低速和高速延迟。 P偏置控制电压由N偏压控制电压由闭环电压控制电路产生。 还描述了并入一个或多个对称CMOS压控延迟单元的电压控制测力传感器，集成电路，电子系统和数据处理系统。
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公开(公告)号：US5623644A
公开(公告)日：1997-04-22
申请号：US296019
申请日：1994-08-25
申请人： Keith-Michael W. Self , Shekhar Y. Borkar , Jerry G. Jex , Edward A. Burton , Stephen R. Mooney , Prantik K. Nag
发明人： Keith-Michael W. Self , Shekhar Y. Borkar , Jerry G. Jex , Edward A. Burton , Stephen R. Mooney , Prantik K. Nag
IPC分类号： G06F15/173 , G06F13/00 , G06F15/16
CPC分类号： G06F15/17381
摘要： A unidirectional point-to-point communication apparatus for communicating messages between two computing resources irrespective of the phase of the messages, length of a communication path between the two computing resources and internal speed of the two computing resources. The communication apparatus has a high speed communication bus coupling a transmitter and a receiver for transmitting the messages from the transmitter to the receiver. A high speed communication clock is coupled to the bus and the receiver for timing the messages transmitted on the high speed communication bus between transmitter and the receiver. A large data buffer is coupled to the high speed communication bus after the receiver for storing messages transmitted between the transmitter and the receiver. A buffer accessing circuit is coupled to the buffer for referencing write locations to store the messages received from the transmitter over the communication bus, and for referencing read locations for reading the messages out of the buffer by the receiver. Finally, a delay locked loop circuit is coupled to the communication bus, the buffer accessing circuit and the buffer for providing the proper set-up and hold time requirements for the messages transmitted on the communication bus from the transmitter and storing the messages in the buffer.
摘要翻译： 一种单向点对点通信装置，用于在两个计算资源之间传送消息，而不管消息的相位，两个计算资源之间的通信路径的长度以及两个计算资源的内部速度。 通信装置具有耦合发射机和接收机的高速通信总线，用于将消息从发射机发射到接收机。 高速通信时钟耦合到总线和接收器，用于定时在发射机和接收机之间的高速通信总线上发送的消息。 在用于存储在发射机和接收机之间传输的消息的接收机之后，大数据缓冲器耦合到高速通信总线。 缓冲器访问电路耦合到缓冲器，用于参考写入位置以存储通过通信总线从发送器接收的消息，并且用于参考由接收器读出缓冲器中的消息的读取位置。 最后，延迟锁定环路电路耦合到通信总线，缓冲器访问电路和缓冲器，用于为在通信总线上从发送器发送的消息提供适当的建立和保持时间要求，并将消息存储在缓冲器中 。
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公开(公告)号：US5604450A
公开(公告)日：1997-02-18
申请号：US508159
申请日：1995-07-27
IPC分类号： H03K5/02 , H03K19/0175 , H03K19/00
CPC分类号： H03K19/01759 , H03K5/026
摘要： In a computer system having multiple components, a bidirectional scheme which allows bidirectional data communications between components over a single wire without using termination resistors by placing two drivers from two corresponding processor cores on the same wire, and allowing simultaneous data transfer in two directions. This doubles the effective bandwidth per pin without requiring a modification to the clocking scheme of the system. The driver is impedance matched to the line, and used as the termination for the driver on the opposite end of the wire. This reduces the termination power, since no power is consumed when both drivers are in the same state. The bidirectional flow of data creates a ternary encoding, with a relatively simple decoding possible.
摘要翻译： 在具有多个组件的计算机系统中，双向方案允许通过单个线路在组件之间进行双向数据通信而不使用终端电阻器，通过将来自两个对应的处理器核心的两个驱动器放置在相同的线路上，并允许在两个方向上同时进行数据传输。 这可以使每个引脚的有效带宽增加一倍，而不需要修改系统的时钟方案。 驱动器与线路阻抗匹配，并用作线缆另一端的驱动器终端。 这降低了终端功率，因为当两个驱动器处于相同状态时都不消耗电力。 数据的双向流创建三进制编码，可以使用相对简单的解码。
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公开(公告)号：US5546023A
公开(公告)日：1996-08-13
申请号：US494486
申请日：1995-06-26
申请人： Shekhar Borkar , Stephen R. Mooney
发明人： Shekhar Borkar , Stephen R. Mooney
CPC分类号： G06F1/10
摘要： A daisy chained clock distribution scheme for distributing a clock signal from a central communications clock driver to the nodes of a massively parallel multi-processor computer or supercomputer. The daisy chained clocking scheme is implemented using point-to-point clock distribution of a differential clock signal to the communication nodes of a plurality of processors in a multicomputer system or to components connected to a common bus in a high speed microprocessor system. Differential signaling is employed wherein the differentiality is maintained including through silicon. In an alternate embodiment, the clock pulse is also regenerated in each node component.
摘要翻译： 一种用于将时钟信号从中央通信时钟驱动器分配到大规模并行多处理器计算机或超级计算机的节点的菊花链时钟分配方案。 菊花链接计时方案通过差分时钟信号的点对点时钟分配实现到多计算机系统中的多个处理器的通信节点或连接到高速微处理器系统中的公共总线的组件。 使用差分信号，其中通过硅保持微分。 在替代实施例中，时钟脉冲也在每个节点组件中再生。
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公开(公告)号：US07177205B2
公开(公告)日：2007-02-13
申请号：US10833966
申请日：2004-04-27
IPC分类号： G11C11/4193
CPC分类号： H03L7/0812
摘要： In some embodiments, a chip includes a chip interface to accept a delay control signal from outside the chip. The chip also includes a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal. Other embodiments are described and claimed.
摘要翻译： 在一些实施例中，芯片包括用于从芯片外部接收延迟控制信号的芯片接口。 芯片还包括可控延迟线，以响应于延迟控制信号来延迟输入信号，以提供具有与输入信号的特定相位关系的输出信号。 描述和要求保护其他实施例。
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公开(公告)号：US06812757B2
公开(公告)日：2004-11-02
申请号：US10146689
申请日：2002-05-14
IPC分类号： H03L706
CPC分类号： H03F3/45219 , H03D13/003 , H03F3/45183 , H03F2203/45318 , H03F2203/45394 , H03F2203/45674 , H03L7/091
摘要： A phase lock loop circuit including a voltage controlled oscillator and a phase detector having a sampling circuit and a linear voltage-to-current converter to create a control voltage for the voltage controlled oscillator. The phase lock loop circuit comprising a voltage-to-current circuit to influence a voltage on a capacitor, the voltage controlled oscillator responsive to the voltage on the capacitor, and the sampling circuit responsive to the first and second clock signals to generate two voltage values.
摘要翻译： 一种锁相环电路，包括压控振荡器和具有采样电路和线性电压 - 电流转换器的相位检测器，以产生用于压控振荡器的控制电压。 所述锁相环电路包括用于影响电容器上的电压的电压 - 电流电路，所述压控振荡器响应于所述电容器上的电压，所述采样电路响应于所述第一和第二时钟信号以产生两个电压值 。
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公开(公告)号：US06803790B2
公开(公告)日：2004-10-12
申请号：US10690235
申请日：2003-10-21
IPC分类号： H03K190175
CPC分类号： G06F13/4077
摘要： A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a clock circuit. The synchronization and clock circuit synchronizes the port with another simultaneous data port coupled to the same bus. A clock driver circuit is provided that is capable of being turned on and off. Prior to synchronization, the clock driver is off, and after synchronization, the clock driver is on. A clock receiver circuit includes a clock detection circuit to detect the presence of an input clock signal. When an integrated circuit is ready to communicate, the output clock driver is turned on and the clock detection circuit is monitored to determine when an input clock signal is received. When both the output clock driver is turned on, and an input clock signal is being received, the simultaneous bidirectional port is synchronized, and communication between integrated circuits can take place.
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公开(公告)号：US06744287B2
公开(公告)日：2004-06-01
申请号：US10225326
申请日：2002-08-21
IPC分类号： H03K1716
CPC分类号： H04L25/0292 , H03K17/164 , H04L5/1423 , H04L25/0278 , H04L25/028
摘要： A bi-directional communication system includes a driver capable of controlling a slew rate of transmitted data signals. Impedance matching can be provided to match an impedance of a driver circuit to an impedance of a communication line. The impedance is maintained constant as data is driven from the data driver. The data receiver circuit can adjust a reference voltage in response to simultaneously transmitted data. The slew rate of the receiver circuit trip point is controlled to maintain adequate noise margin during operation. Both the receiver and driver circuits can be controlled using a delay line circuit.
摘要翻译： 双向通信系统包括能够控制发送的数据信号的转换速率的驱动器。 可以提供阻抗匹配以将驱动器电路的阻抗与通信线路的阻抗相匹配。 当数据从数据驱动器驱动时，阻抗保持不变。 数据接收器电路可以响应于同时发送的数据来调整参考电压。 控制接收器电路跳变点的转换速率，以在运行期间保持足够的噪声容限。 可以使用延迟线电路来控制接收器和驱动器电路。
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公开(公告)号：US06411151B1
公开(公告)日：2002-06-25
申请号：US09459783
申请日：1999-12-13
IPC分类号： G06F104
CPC分类号： G06F1/10 , H03K5/2481
摘要： A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.
摘要翻译： 公开了一种低抖动外部时钟系统和方法。 根据本发明的一个实施例，在第一时钟信号线和第二时钟信号线上接收差分时钟信号。 耦合到第一时钟信号线和第二时钟信号线的差分放大器将差分时钟信号放大成单端输出时钟信号。
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80.发明授权公开(公告)号：US06348811B1
公开(公告)日：2002-02-19
申请号：US09605479
申请日：2000-06-28
IPC分类号： H03L1900
CPC分类号： H04L1/243
摘要： A simultaneous bi-directional I/O circuit includes a first MUX in the reference select circuitry and a second, matching MUX in the pre-driver stage of the output buffer. In normal mode, the first MUX passes the driven data output signal, which controls the threshold of the differential receiver circuit between two different non-zero voltage levels, so that the receiver circuit can properly decode an incoming signal at the I/O node or pin. In an AC switching state or loopback test mode, the first MUX deselects the driven data output signal from controlling the receiver circuit. This allows the receiver circuit to decode outgoing data that is being looped back as incoming data. The second MUX enables the reference select circuitry to switch at a rate that matches the output slew rate in order to provide high-speed operation. Also described are an electronic system, a data processing system, and various methods of testing simultaneous bi-directional I/O circuits.
摘要翻译： 同时双向I / O电路包括参考选择电路中的第一MUX和输出缓冲器的前驱动器级中的第二匹配MUX。 在正常模式下，第一MUX通过驱动数据输出信号，该信号控制差分接收器电路的阈值在两个不同的非零电压电平之间，使得接收机电路可以正确地解码I / O节点处的输入信号， 销。 在交流切换状态或环回测试模式中，第一MUX从控制接收机电路中取消选择驱动数据输出信号。 这允许接收器电路将作为输入数据循环的输出数据进行解码。 第二MUX使参考选择电路以与输出转换速率匹配的速率切换，以便提供高速操作。 还描述了电子系统，数据处理系统和测试同时双向I / O电路的各种方法。
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