Voltage to current converter
    1.
    发明授权
    Voltage to current converter 有权
    电压到电流转换器

    公开(公告)号:US06420912B1

    公开(公告)日:2002-07-16

    申请号:US09735858

    申请日:2000-12-13

    IPC分类号: H02M1100

    摘要: A voltage-to-current circuit utilizes an NMOS-input voltage-to-current (V-I) converter and a PMOS-input V-I converter, with both driving a common gate output stage. Each of the V-I converters includes a transconductance amplifier and a current mirror. The common gate output stage includes two series connected complementary pairs of transistors. One complementary pair drives the output, and the other complementary pair biases the first. The V-I circuit can be utilized as part of a phase detector, which is in turn can be utilized as part of a phase lock loop or a delay lock loop.

    摘要翻译: 电压 - 电流电路使用NMOS输入电压 - 电流(V-I)转换器和PMOS输入V-I转换器,同时驱动公共栅极输出级。 每个V-I转换器包括跨导放大器和电流镜。 公共栅极输出级包括两个串联的互补晶体管对。 一对互补对驱动输出,另一个互补对偏置第一个。 V-I电路可以用作相位检测器的一部分,相位检测器又可以用作锁相环或延迟锁定环路的一部分。

    Phase lock loop apparatus
    2.
    发明授权
    Phase lock loop apparatus 失效
    锁相环装置

    公开(公告)号:US06812757B2

    公开(公告)日:2004-11-02

    申请号:US10146689

    申请日:2002-05-14

    IPC分类号: H03L706

    摘要: A phase lock loop circuit including a voltage controlled oscillator and a phase detector having a sampling circuit and a linear voltage-to-current converter to create a control voltage for the voltage controlled oscillator. The phase lock loop circuit comprising a voltage-to-current circuit to influence a voltage on a capacitor, the voltage controlled oscillator responsive to the voltage on the capacitor, and the sampling circuit responsive to the first and second clock signals to generate two voltage values.

    摘要翻译: 一种锁相环电路,包括压控振荡器和具有采样电路和线性电压 - 电流转换器的相位检测器,以产生用于压控振荡器的控制电压。 所述锁相环电路包括用于影响电容器上的电压的电压 - 电流电路,所述压控振荡器响应于所述电容器上的电压,所述采样电路响应于所述第一和第二时钟信号以产生两个电压值 。

    Differential delay cell with common delay control and power supply
    4.
    发明授权
    Differential delay cell with common delay control and power supply 失效
    具有通用延迟控制和电源的差分延迟单元

    公开(公告)号:US06351191B1

    公开(公告)日:2002-02-26

    申请号:US09584565

    申请日:2000-05-31

    IPC分类号: H03B524

    摘要: A differential delay cell includes load transistors and a current source transistor biased linearly. The delay control input of the differential delay cell is also the power supply input such that when the power supply voltage changes, the delay in the differential delay cell changes. The resistance presented by the load transistors changes as a function of the power supply voltage, as does the current sourced by the variable current source. The combination of changing resistance and changing current as the power supply voltage changes results in a substantially constant output voltage swing. A ring of differential delay cells is included in a voltage controlled oscillator, which is in turn included in a phase lock loop. The phase lock loop has a wide loop bandwidth and the voltage controlled oscillator has a good power supply rejection ratio.

    摘要翻译: 差分延迟单元包括负载晶体管和线性偏置的电流源晶体管。 差分延迟单元的延迟控制输入也是电源输入,使得当电源电压变化时,差分延迟单元中的延迟变化。 由负载晶体管提供的电阻随着电源电压的变化而变化,与可变电流源的电流一样。 随着电源电压变化,电阻变化和电流变化的组合导致基本恒定的输出电压摆幅。 差分延迟单元的环包括在压控振荡器中,其又包括在锁相环中。 锁相环具有宽环路带宽,压控振荡器具有良好的电源抑制比。

    Low jitter external clocking
    5.
    发明授权
    Low jitter external clocking 有权
    低抖动外部时钟

    公开(公告)号:US06798265B2

    公开(公告)日:2004-09-28

    申请号:US10132599

    申请日:2002-04-25

    IPC分类号: G06F104

    CPC分类号: G06F1/10 H03K5/2481

    摘要: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

    摘要翻译: 公开了一种低抖动外部时钟系统和方法。 根据本发明的一个实施例,在第一时钟信号线和第二时钟信号线上接收差分时钟信号。 耦合到第一时钟信号线和第二时钟信号线的差分放大器将差分时钟信号放大成单端输出时钟信号。

    Low jitter differential amplifier with negative hysteresis
    6.
    发明授权
    Low jitter differential amplifier with negative hysteresis 失效
    具有负滞后的低抖动差分放大器

    公开(公告)号:US06377108B1

    公开(公告)日:2002-04-23

    申请号:US09649257

    申请日:2000-08-28

    IPC分类号: H03K1776

    CPC分类号: H03K5/088

    摘要: A differential amplifier is provided, incorporating negative hysteresis by automatic reference voltage adjustment. A delayed output signal is routed to a switch or multiplexer which functions to select one of two reference voltage levels, creating negative hysteresis. The delayed output signal is delayed by a series of inverters, which prevent certain embodiments of the invention from oscillating under some conditions. The two reference voltage levels are selected to be near the respective data signal input high and low signal voltage levels, but far enough from these levels so as not to be adversely affected by noise or other interference.

    摘要翻译: 提供了一个差分放大器,通过自动参考电压调整结合了负滞后。 延迟的输出信号被路由到开关或多路复用器,其用于选择两个参考电压电平之一,产生负的滞后。 延迟的输出信号由一系列逆变器延迟,这防止本发明的某些实施例在某些情况下振荡。 两个参考电压电平被选择为接近相应的数据信号输入高和低信号电压电平,但远离这些电平,以免受噪声或其他干扰的不利影响。

    Complementary input self-biased differential amplifier with gain compensation
    7.
    发明授权
    Complementary input self-biased differential amplifier with gain compensation 有权
    具有增益补偿的互补输入自偏置差分放大器

    公开(公告)号:US06304141B1

    公开(公告)日:2001-10-16

    申请号:US09609495

    申请日:2000-06-30

    IPC分类号: H03F345

    摘要: A complementary input self-biased differential amplifier includes gain compensation devices. The gain compensation devices are in parallel with input transistors and are biased by a self-bias node. The gain control devices serve to keep current flowing in load devices when operating at common-mode extremes, thereby limiting the reduction in amplifier output impedance and limiting the corresponding reduction in differential-mode gain at common-mode extremes. The gain control devices also serve to reduce input stage transconductance near the center of the common-mode input voltage swing, thereby reducing differential-mode gain near the center of the swing, and reducing gain variations across the input common-mode range. The differential amplifier can include multiple input legs on either side of an input stage. Multiple legs allow multiple reference voltages to be compared to a data signal. A bidirectional data link utilizes the multiple reference inputs to remove an ambiguity created by the bidirectional data link.

    摘要翻译: 互补输入自偏置差分放大器包括增益补偿装置。 增益补偿装置与输入晶体管并联并由自偏压节点偏置。 增益控制装置用于在共模极端工作时保持电流在负载装置中流动,从而限制了放大器输出阻抗的减小,并限制了共模极限下差分模式增益的相应降低。 增益控制装置还用于减小共模输入电压摆幅中心附近的输入级跨导,从而减小摆幅中心附近的差模增益,并减少输入共模范围内的增益变化。 差分放大器可以包括输入级两侧的多个输入支路。 多个支路允许将多个参考电压与数据信号进行比较。 双向数据链路利用多个参考输入来消除由双向数据链路创建的歧义。

    Low jitter external clocking
    8.
    发明授权
    Low jitter external clocking 有权
    低抖动外部时钟

    公开(公告)号:US06411151B1

    公开(公告)日:2002-06-25

    申请号:US09459783

    申请日:1999-12-13

    IPC分类号: G06F104

    CPC分类号: G06F1/10 H03K5/2481

    摘要: A low jitter external clocking system and method are disclosed. According to one embodiment of the present invention, a differential clock signal is received on a first clock signal line and a second clock signal line. A differential amplifier coupled to the first clock signal line and the second clock signal line amplifies the differential clock signal into a single-ended output clock signal.

    摘要翻译: 公开了一种低抖动外部时钟系统和方法。 根据本发明的一个实施例,在第一时钟信号线和第二时钟信号线上接收差分时钟信号。 耦合到第一时钟信号线和第二时钟信号线的差分放大器将差分时钟信号放大成单端输出时钟信号。

    IN-SITU JITTER TOLERANCE TESTING FOR SERIAL INPUT OUTPUT
    9.
    发明申请
    IN-SITU JITTER TOLERANCE TESTING FOR SERIAL INPUT OUTPUT 有权
    用于串行输入输出的IN-SITU JITTER耐力测试

    公开(公告)号:US20090310728A1

    公开(公告)日:2009-12-17

    申请号:US12139835

    申请日:2008-06-16

    IPC分类号: H04L7/00

    CPC分类号: G01R31/31708 H04L7/033

    摘要: According to some embodiments, a method and apparatus are provided to generate a sine wave via a jitter modulator to modulate a control voltage of a clock source. The jitter modulator is in-situ on a die. The sine wave is received at a clock and data recovery circuit comprising the clock source. The clock and data recovery circuit is in-situ on the die.

    摘要翻译: 根据一些实施例,提供了一种方法和装置,用于经由抖动调制器产生正弦波,以调制时钟源的控制电压。 抖动调制器在芯片上原位置。 在包括时钟源的时钟和数据恢复电路中接收正弦波。 时钟和数据恢复电路就位于芯片上。

    Adaptive equalization using a conditional update sign-sign least mean square algorithm
    10.
    发明授权
    Adaptive equalization using a conditional update sign-sign least mean square algorithm 有权
    使用条件更新符号最小均方算法进行自适应均衡

    公开(公告)号:US07289557B2

    公开(公告)日:2007-10-30

    申请号:US10660228

    申请日:2003-09-10

    IPC分类号: H03D3/22 H04L27/22

    摘要: An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: h(t+1)= h(t)+μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{ x(t)}, where h(t) is the filter vector representing the filter taps of the FIR filter, x(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, μ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.

    摘要翻译: 用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应(FIR)滤波器,其中通过执行更新的电路在训练序列期间迭代地更新滤波器:<?in-line-formula description =“In-line 公式“end =”lead“?> h(t + 1)= h(t)+ mu [sgn {d(t)} - t)-Kd(t)}] sgn { x(t)},<?in-line-formula description =“In-line Formulas”end =“tail”?> OSTYLE =“SINGLE”> h(t)是表示FIR滤波器的滤波器抽头的滤波器向量,x(t)是表示接收数据的当前和过去采样的数据x(t) t),d(t)是用于训练的期望数据,z(t)是FIR滤波器的输出,mu决定适配的存储器或窗口大小,K是考虑到实际限制的比例因子 通信信道,接收机和均衡器。 此外,提供了用于校准比例因子K的过程和电路结构。