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公开(公告)号：US07146613B2
公开(公告)日：2006-12-05
申请号：US10157530
申请日：2002-05-29
CPC分类号： G06F9/45504 , G06F8/4434
摘要： A digital system and method of operation is which the digital system has a processor with a virtual machine environment for interpretively executing instructions. First, a sequence of instructions is received (404) for execution by the virtual machine. The sequence of instructions is examined (408–414) to determine if a certain type of iterative sequence is present. If the certain type of iterative sequence is present, the iterative sequence is replaced (412) with a proprietary code sequence. After the modifications are complete, the modified sequence is executed in a manner that a portion of the sequence of instructions is executed in an interpretive manner (418); and the proprietary code sequences are executed directly by acceleration circuitry (420).
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公开(公告)号：US07120715B2
公开(公告)日：2006-10-10
申请号：US09932866
申请日：2001-08-17
IPC分类号： G06F13/14
CPC分类号： G06F12/1027 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F9/5094 , G06F9/52 , G06F12/0292 , G06F12/0879 , G06F12/0891 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2209/5014 , G06F2209/5021 , G06F2212/1028 , Y02D10/13 , Y02D10/22 , Y02D10/24
摘要： A digital system and method of operation is provided in which several processors (740(0)–740(n)) are connected to a shared resource (750). Each processor has an access priority register (1410) that is loaded with an access priority value by software executing on the processor. A memory management unit (MMU) (700) is connected to receive a request address (742) from each respective processor. The MMU has a set of entries that correspond to pages of address space. Each entry provides a set of attributes for the associated page of address space, including an address space priority value 309a. For each request, the MMU accesses an entry corresponding to the request address and provides an address space priority value associated with that requested address space page. Arbitration circuitry (1430) is connected to receive a request signal from each processor along with the access priority value from each access priority register and the address space priority value from each MMU. The arbitration circuitry is operable to schedule access to the shared resource according to higher of the pair of priority values provided by each processor.
摘要翻译： 提供了数字系统和操作方法，其中若干处理器（740（0）-704（n））连接到共享资源（750）。 每个处理器具有通过在处理器上执行的软件加载访问优先级值的访问优先级寄存器（1410）。 存储器管理单元（MMU）（700）被连接以从每个相应的处理器接收请求地址（742）。 MMU具有一组对应于地址空间页面的条目。 每个条目为相关联的地址空间页面提供一组属性，包括地址空间优先级值309a。 对于每个请求，MMU访问与请求地址相对应的条目，并提供与该请求的地址空间页相关联的地址空间优先级值。 连接仲裁电路（1430），从每个处理器接收来自每个访问优先级寄存器的访问优先级值和来自每个MMU的地址空间优先级值的请求信号。 仲裁电路可操作以根据由每个处理器提供的优先级对中的较高者调度对共享资源的访问。
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公开(公告)号：US20060026412A1
公开(公告)日：2006-02-02
申请号：US11186036
申请日：2005-07-21
IPC分类号： G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second group of instructions in lieu of the individual instruction.
摘要翻译： 一种电子设备，包括包括单独指令和第一组指令的处理器。 该设备还包括外部耦合到处理器的存储器以及第二组指令。 当执行时，第一组指令使得处理器执行第二组指令来代替单独的指令。
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公开(公告)号：US20060026398A1
公开(公告)日：2006-02-02
申请号：US11116918
申请日：2005-04-28
IPC分类号： G06F9/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012 , Y02D10/13
摘要： A processor executes an instruction that causes a source data field from a programmable position within a first source register to be copied to a destination register. The instruction is particularly useful for generating media-based bitstreams (e.g., audio, video). In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.
摘要翻译： 处理器执行使来自第一源寄存器中的可编程位置的源数据字段被复制到目的地寄存器的指令。 该指令对于生成基于媒体的比特流（例如，音频，视频）特别有用。 在一些实施例中，系统（例如，诸如蜂窝电话的通信设备）包括能够执行如上所述的指令的处理器。
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公开(公告)号：US20060026396A1
公开(公告)日：2006-02-02
申请号：US11116893
申请日：2005-04-28
IPC分类号： G06F9/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012 , Y02D10/13
摘要： A processor executes a load (or store) instruction that permits optional error checking to be performed. Based on a control bit in the load instruction, the processor executes the load instruction by causing contents of a source register to be compared to a predetermined value. If the contents of the source register equals the predetermined value, the processor executes an exception handler. However, if the source register contents differs from the predetermined value, the load instruction causes the processor to cause a data value from memory to be loaded into a destination register
摘要翻译： 处理器执行允许执行可选错误检查的加载（或存储）指令。 基于加载指令中的控制位，处理器通过使源寄存器的内容与预定值进行比较来执行加载指令。 如果源寄存器的内容等于预定值，则处理器执行异常处理程序。 然而，如果源寄存器内容与预定值不同，则加载指令使处理器将来自存储器的数据值加载到目的寄存器
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公开(公告)号：US20060026391A1
公开(公告)日：2006-02-02
申请号：US11188827
申请日：2005-07-25
IPC分类号： G06F9/30
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A processor that comprises decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, the single instruction requiring an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit and stores the operand to the second storage unit for use by the group of instructions.
摘要翻译： 一种处理器，包括耦合到第一存储单元并包括数据结构的解码逻辑。 处理器还包括耦合到解码逻辑的第二存储单元。 解码逻辑从第一存储单元获得单个指令，并且如果由数据结构中的第一位指示，则代替单个指令处理一组指令，需要操作数的单个指令。 如果由数据结构中的第二位指示，则解码逻辑从第一存储单元获得操作数，并将操作数存储到第二存储单元以供指令组使用。
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公开(公告)号：US20060026370A1
公开(公告)日：2006-02-02
申请号：US11186271
申请日：2005-07-21
IPC分类号： G06F12/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.
摘要翻译： 提供了用于在Java应用程序中访问间接内存的系统，方法和存储介质。 在一些实施例中，提供存储介质，其包括在设备的间接存储器上执行一个或多个操作的Java应用软件。 软件包括创建表示间接存储器的Java类的实例的指令以及使用存储器元件的元素唯一标识符（“euid”）访问间接存储器的存储器元件的指令。 其他实施例提供了一种用于访问设备的存储器元件的方法，包括创建表示存储器元件的Java类的实例，以及使用存储元件的元素唯一标识符（“euid”）访问存储器元件的存储器元件， 其中所述存储器元件未映射到所述处理器的数据存储器空间。
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78.发明授权Dynamic hardware configuration for energy management systems using task attributes 有权使用任务属性的能源管理系统的动态硬件配置公开(公告)号：US06889330B2
公开(公告)日：2005-05-03
申请号：US09932354
申请日：2001-08-17
CPC分类号： G06F9/4893 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F9/30043 , G06F11/3409 , G06F12/0292 , G06F12/0879 , G06F12/0891 , G06F12/1027 , G06F12/1081 , G06F2201/81 , G06F2201/88 , G06F2201/885 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D10/16 , Y02D10/172 , Y02D10/24 , Y02D10/34 , Y10T307/461
摘要： A multiprocessor system (10) includes a plurality of processing modules, such as MPUs (12), DSPs (14), and coprocessors/DMA channels (16). Power management software (38) in conjunction with profiles (36) for the various processing modules and the tasks to executed are used to build scenarios which meet predetermined power objectives, such as providing maximum operation within package thermal constraints or using minimum energy. Actual activities associated with the tasks are monitored during operation to ensure compatibility with the objectives. The allocation of tasks may be changed dynamically to accommodate changes in environmental conditions and changes in the task list. As each task in a scenario is executed, a control word associated with the task can be used to enable/disable circuitry, or to set circuits to an optimum configuration.
摘要翻译： 多处理器系统（10）包括多个处理模块，例如MPU（12），DSP（14）和协处理器/ DMA通道（16）。 电力管理软件（38）结合用于各种处理模块的简档（36）和执行的任务被用于构建满足预定功率目标的场景，例如在封装热约束内提供最大操作或使用最小能量。 在操作过程中监视与任务相关的实际活动，以确保与目标的兼容性。 可以动态地改变任务的分配，以适应环境条件的变化和任务列表的变化。 当执行场景中的每个任务时，可以使用与该任务相关联的控制字来启用/禁用电路，或者将电路设置为最佳配置。
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79.发明授权
公开(公告)号：US6085308A
公开(公告)日：2000-07-04
申请号：US989387
申请日：1997-12-12
申请人： Gerard Chauvel , Francis Aussedat , Pierre Calippe
发明人： Gerard Chauvel , Francis Aussedat , Pierre Calippe
CPC分类号： G06F9/3879 , G06F9/30018 , G06F9/3877
摘要： Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor comprises a program part (30) including an incrementation register (31), a program memory (33) connected to the incrementation register (31) in order to receive addresses thereof, a decoding part (35) intended to receive instructions from the program memory (33) of the program part (30) with a view to executing an instruction in two cycles, and a data part (36) for executing the instruction.
摘要翻译： 旨在与系统的至少一个主处理器相关联的协议处理器，以便执行主处理器不适合的任务。 协议处理器包括一个包括递增寄存器（31）的程序部分（30），连接到增量寄存器（31）以便接收地址的程序存储器（33），用于接收来自 程序部分（30）的程序存储器（33），用于执行两个周期的指令，以及用于执行指令的数据部分（36）。
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公开(公告)号：US5544104A
公开(公告)日：1996-08-06
申请号：US404409
申请日：1995-03-14
申请人： Gerard Chauvel
发明人： Gerard Chauvel
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/108 , H04L49/1576 , H04Q11/0478 , H04L2012/5681
摘要： An interconnection-point memory which includes an array of N1 input buses (Rj) intended to be connected to a first plurality of N1 data-sender devices, an array of N2 output buses (Ck) intended to be connected to a second plurality of N2 data-receiver devices, and interconnection means (17) for connecting the array of input buses to the array of output buses. The interconnection means include on the one hand, a third plurality of N3 switching memories (FIFO m) used as first-in, first-out FIFO devices provided with a write port (Din) and with a read port (Dout), and on the other hand, first control means (S[j,m],24a,24b) for connecting in a virtual manner the input port of at least one switching memory to a specified input bus, and second control means (S[k,m],24a',24b') for connecting in a virtual manner at least one output bus to the read port of the said switching memory, so that the said specified switching memory constitutes a temporary interconnection point, independent of the input buses and output buses to be interconnected. This interconnection-point memory enables Application to the asynchronous transfer of data between senders and receivers.
摘要翻译： 一种互连点存储器，其包括旨在连接到第一多个N1数据发送器设备的N1输入总线阵列（Rj），旨在连接到第二多个N2的N2输出总线（Ck）的阵列 数据接收设备和用于将输入总线阵列连接到输出总线阵列的互连装置（17）。 互连装置一方面包括第三多个N3切换存储器（FIFO m），其被用作设置有写入端口（Din）和读取端口（Dout）的先进先出FIFO设备，并且接通 另一方面，用于以虚拟方式将至少一个切换存储器的输入端口连接到指定的输入总线的第一控制装置（S [j，m]，24a，24b）和第二控制装置（S [k，m ]，24a'，24b'），用于以虚拟的方式将至少一个输出总线连接到所述切换存储器的读取端口，使得所述指定的开关存储器构成临时互连点，独立于输入总线和输出总线 互连。 该互连点存储器使应用程序能够在发送方和接收方之间异步传输数据。
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