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    MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION
    75.
    发明申请
    MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION 有权
    通过选择性沉积的微电子结构

    公开(公告)号：US20090072317A1

    公开(公告)日：2009-03-19

    申请号：US12273894

    申请日：2008-11-19

    申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7851 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78645

    摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

    摘要翻译： finFET结构包括位于衬底上的半导体鳍片。 栅电极穿过半导体鳍片。 栅电极具有邻接其侧壁的间隔层。 间隔层不完全覆盖半导体鳍片的侧壁。 栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上而不是在基底的相邻表面上，使得间隔层不完全覆盖 半导体鳍片 可以使用侧向生长方法制造其它微电子结构。

    METHODS FOR FORMING SELF-ALIGNED BORDERLESS CONTACTS FOR STRAIN ENGINEERED LOGIC DEVICES AND STRUCTURE THEREOF
    76.
    发明申请
    METHODS FOR FORMING SELF-ALIGNED BORDERLESS CONTACTS FOR STRAIN ENGINEERED LOGIC DEVICES AND STRUCTURE THEREOF 有权
    用于形成用于应变工程逻辑器件的自对准无边界接触的方法及其结构

    公开(公告)号：US20090057730A1

    公开(公告)日：2009-03-05

    申请号：US11850172

    申请日：2007-09-05

    申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66545 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/6659 ,  H01L29/7833

    摘要： A method for forming a borderless contact for a semiconductor FET (Field Effect Transistor) device, the method comprising, forming a gate conductor stack on a substrate, forming spacers on the substrate, such that the spacers and the gate conductor stack partially define a volume above the gate conductor stack, wherein the spacers are sized to define the volume such that a stress liner layer deposited on the gate conductor stack substantially fills the volume, depositing a liner layer on the substrate, the spacers, and the gate conductor stack, depositing a dielectric layer on the liner layer, etching to form a contact hole in the dielectric layer, etching to form the contact hole in the liner layer, such that a portion of a source/drain diffusion area formed in the substrate is exposed and depositing contact metal in the contact hole.

    摘要翻译： 一种用于形成半导体FET（场效应晶体管）器件的无边界接触的方法，所述方法包括：在衬底上形成栅极导体堆叠，在衬底上形成间隔物，使得间隔物和栅极导体堆叠部分地限定体积 在栅极导体堆叠之上，其中间隔物的尺寸设定成限定体积，使得沉积在栅极导体堆叠上的应力衬垫层基本上填充体积，在衬底，间隔物和栅极导体堆叠上沉积衬垫层，沉积 衬底层上的电介质层，蚀刻以在电介质层中形成接触孔，蚀刻以在衬垫层中形成接触孔，使得在衬底中形成的源极/漏极扩散区域的一部分被暴露并沉积接触 接触孔中的金属。

    Double-gate FETs (Field Effect Transistors)
    79.
    发明授权
    Double-gate FETs (Field Effect Transistors) 失效
    双栅极FET（场效应晶体管）

    公开(公告)号：US07250347B2

    公开(公告)日：2007-07-31

    申请号：US10905979

    申请日：2005-01-28

    申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit

    发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/78654

    摘要： A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.

    摘要翻译： 一种用于形成具有相互对准的双栅极的晶体管的方法。 该方法包括以下步骤：（a）提供环绕栅极晶体管结构，其中环绕栅极晶体管结构包括（i）半导体区域和（ii）围绕半导体区域包围的栅电极区域，其中 栅电极区域通过栅极电介质膜与半导体区域电绝缘; 以及（b）去除环绕栅极晶体管结构的第一和第二部分，以便从栅极电极区域形成顶部和底部栅电极，其中顶部和底部栅电极彼此电断开。