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公开(公告)号:US10262733B2
公开(公告)日:2019-04-16
申请号:US15325543
申请日:2014-10-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Jianhua Yang , Miao Hu , John Paul Strachan , Ning Ge
Abstract: A memristive dot-product system for vector processing is described. The memristive dot-product system includes a crossbar array having a number of memory elements. Each memory element includes a memristor. Each memory element includes a transistor. The system also includes a vector input register. The system also includes a vector output register.
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公开(公告)号:US20190043573A1
公开(公告)日:2019-02-07
申请号:US16073922
申请日:2016-02-24
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Brent Buchanan , Le Zheng , John Paul Strachan
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/2297 , G11C13/0002 , G11C13/0007 , G11C13/0021 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/0038 , G11C13/004 , G11C29/50012 , G11C2013/0045 , G11C2013/0071 , G11C2013/0073 , G11C2213/79
Abstract: In one example in accordance with the present disclosure a control circuit is described. The control circuit includes a source following component to receive an input voltage and output a switching voltage. The circuit also includes an input leg of a current mirror coupled to the source following component. The input leg of the current mirror replicates the switching voltage to an output leg of the current mirror of a memristive bit cell. The circuit also includes a number of current control components. At least one of the current control components enforces a constant current through the source following component and other current control components maintain the input leg of the current mirror and the output leg of the current mirror at the same current.
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公开(公告)号:US20180314927A1
公开(公告)日:2018-11-01
申请号:US15770430
申请日:2015-10-30
Applicant: Hewlett Packard Enterprise Development LP
CPC classification number: G06N3/063 , G06N3/0635
Abstract: According to an example, a hybrid synaptic architecture based neural network may be implemented by determining, from input data, information that is to be recognized, mined, and/or synthesized by a plurality of analog neural cores. Further, the hybrid synaptic architecture based neural network may be implemented by determining, based on the information, selected ones of the plurality of analog neural cores that are to be actuated to identify a data subset of the input data to generate, based on the analysis of the data subset, results of the recognition, mining, and/or synthesizing of the information.
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公开(公告)号:US10109348B2
公开(公告)日:2018-10-23
申请号:US15522364
申请日:2014-10-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Miao Hu , Jianhua Yang , John Paul Strachan , Ning Ge
Abstract: A double bias dot-product engine for vector processing is described. The dot product engine includes a crossbar array having N×M memory elements to store information corresponding to values contained in an N×M matrix, each memory element being a memristive storage device. First and second vector input registers including N voltage inputs, each voltage input corresponding to a value contained in a vector having N×1 values. The vector input registers are connected to the crossbar array to supply voltage inputs to each of N row electrodes at two locations along the electrode. A vector output register is also included to receive voltage outputs from each of M column electrodes.
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公开(公告)号:US09847124B2
公开(公告)日:2017-12-19
申请号:US15500500
申请日:2015-04-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Miao Hu , John Paul Strachan , Ning Ge , Jianhua Yang
CPC classification number: G11C13/0021 , G06F7/588 , G06F17/18 , G06G7/122 , G06N7/005
Abstract: An example apparatus includes a crossbar array of signal lines and control lines. The example apparatus also includes an input controller in circuit with the control lines. The input control is to select one of the control lines. The example apparatus also includes first resistive elements connected between corresponding ones of the control lines and corresponding ones of the signal lines. The first resistive elements have first conductances set to operate as a matrix of probabilities that define a fixed transition kernel of a Markov Chain. The example apparatus also includes second resistive elements in circuit with the signal lines. The second resistive elements have second conductances set to select one of the signal lines exclusive of others of the signal lines based on a subset of the probabilities in the matrix of the probabilities.
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公开(公告)号:US09842646B2
公开(公告)日:2017-12-12
申请号:US15500555
申请日:2015-04-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Miao Hu , Ning Ge , John Paul Strachan , R. Stanley Williams
CPC classification number: G11C13/004 , G06N3/049 , G06N3/0635 , G11C11/54 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C27/005 , G11C2213/74 , G11C2213/75 , G11C2213/76 , G11C2213/79
Abstract: In an example, a memristor apparatus with variable transmission delay may include a first memristor programmable to have one of a plurality of distinct resistance levels, a second memristor, a transistor connected between the first memristor and the second memristor, and a capacitor having a capacitance, in which the capacitor is connected between the first memristor and the transistor. In addition, application of a reading voltage across the second memristor is delayed by a time period equivalent to the programmed resistance level of the first memristor and the capacitance of the capacitor.
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公开(公告)号:US20170221558A1
公开(公告)日:2017-08-03
申请号:US15500555
申请日:2015-04-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Miao Hu , Ning Ge , John Paul Strachan , R. Stanley Williams
IPC: G11C13/00
CPC classification number: G11C13/004 , G06N3/049 , G06N3/0635 , G11C11/54 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/0061 , G11C13/0069 , G11C27/005 , G11C2213/74 , G11C2213/75 , G11C2213/76 , G11C2213/79
Abstract: In an example, a memristor apparatus with variable transmission delay may include a first memristor programmable to have one of a plurality of distinct resistance levels, a second memristor, a transistor connected between the first memristor and the second memristor, and a capacitor having a capacitance, in which the capacitor is connected between the first memristor and the transistor. In addition, application of a reading voltage across the second memristor is delayed by a time period equivalent to the programmed resistance level of the first memristor and the capacitance of the capacitor.
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公开(公告)号:US12254924B2
公开(公告)日:2025-03-18
申请号:US17876471
申请日:2022-07-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor: Giacomo Pedretti , Catherine Graves , Sergey Serebryakov , John Paul Strachan
Abstract: Embodiments of the disclosure provide a system, method, or computer readable medium for providing a differentiable content addressable memory (aCAM) that implements an analog input analog storage and analog output learning memory. The analog output of the differentiable CAM can provide input to a learning algorithm, which may compute the gradients in comparison to historic values and reduce data inaccuracies and power consumption.
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公开(公告)号:US12204961B2
公开(公告)日:2025-01-21
申请号:US18528086
申请日:2023-12-04
Applicant: Hewlett Packard Enterprise Development LP
Inventor: John Paul Strachan , Dejan S. Milojicic , Martin Foltin , Sai Rahul Chalamalasetti , Amit S. Sharma
Abstract: In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.
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公开(公告)号:US12100451B2
公开(公告)日:2024-09-24
申请号:US18326813
申请日:2023-05-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor: Can Li , Catherine Graves , John Paul Strachan
Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.
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