Double bias memristive dot product engine for vector processing

    公开(公告)号:US10109348B2

    公开(公告)日:2018-10-23

    申请号:US15522364

    申请日:2014-10-30

    Abstract: A double bias dot-product engine for vector processing is described. The dot product engine includes a crossbar array having N×M memory elements to store information corresponding to values contained in an N×M matrix, each memory element being a memristive storage device. First and second vector input registers including N voltage inputs, each voltage input corresponding to a value contained in a vector having N×1 values. The vector input registers are connected to the crossbar array to supply voltage inputs to each of N row electrodes at two locations along the electrode. A vector output register is also included to receive voltage outputs from each of M column electrodes.

    Resistive elements to operate as a matrix of probabilities

    公开(公告)号:US09847124B2

    公开(公告)日:2017-12-19

    申请号:US15500500

    申请日:2015-04-23

    CPC classification number: G11C13/0021 G06F7/588 G06F17/18 G06G7/122 G06N7/005

    Abstract: An example apparatus includes a crossbar array of signal lines and control lines. The example apparatus also includes an input controller in circuit with the control lines. The input control is to select one of the control lines. The example apparatus also includes first resistive elements connected between corresponding ones of the control lines and corresponding ones of the signal lines. The first resistive elements have first conductances set to operate as a matrix of probabilities that define a fixed transition kernel of a Markov Chain. The example apparatus also includes second resistive elements in circuit with the signal lines. The second resistive elements have second conductances set to select one of the signal lines exclusive of others of the signal lines based on a subset of the probabilities in the matrix of the probabilities.

    Methods and systems for an analog cam with fuzzy search

    公开(公告)号:US12100451B2

    公开(公告)日:2024-09-24

    申请号:US18326813

    申请日:2023-05-31

    CPC classification number: G11C15/04 G11C15/00

    Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.

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