公开(公告)号：US08116122B2

公开(公告)日：2012-02-14

申请号：US12147723

申请日：2008-06-27

申请人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Kang Yong Kim ,  Dimitar V. Dimitrov ,  Henry F. Huang

发明人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Kang Yong Kim ,  Dimitar V. Dimitrov ,  Henry F. Huang

IPC分类号： G11C11/00

CPC分类号： G11C11/1673 ,  G11C7/06 ,  G11C7/065 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006 ,  Y10S977/933

摘要： A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

摘要翻译： 描述了自旋转移力矩存储装置和自参考读取方案。 读取自旋传递转矩存储单元的一种自参考方法包括：通过磁性隧道结数据单元施加第一读取电流并形成第一位线读取电压，所述磁性隧道结数据单元具有第一电阻状态并存储 第一电压存储装置中的第一位线读取电压。 然后通过磁性隧道结数据单元施加低电阻状态的极化写入电流，形成低的第二电阻状态磁隧道结数据单元。 第二读取电流通过低的第二电阻状态磁隧道结数据单元施加以形成第二位线读取电压。 第二位线读取电压被存储在第二电压存储装置中。 该方法还包括将第一位线读取电压与第二位线读取电压进行比较，以确定磁性隧道结数据单元的第一电阻状态是高电阻状态还是低电阻状态。

公开(公告)号：US20120014175A1

公开(公告)日：2012-01-19

申请号：US13241381

申请日：2011-09-23

申请人： Xiaobin Wang ,  Yiran Chen ,  Alan Wang ,  Haiwen Xi ,  Wenzhong Zhu ,  Hai Li ,  Hongyue Liu

发明人： Xiaobin Wang ,  Yiran Chen ,  Alan Wang ,  Haiwen Xi ,  Wenzhong Zhu ,  Hai Li ,  Hongyue Liu

IPC分类号： G11C11/00 ,  G01R27/14 ,  G01R33/12

CPC分类号： G01R33/098 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/003 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/224 ,  H01L43/08

摘要： A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current.

摘要翻译： 磁存储器件包括具有磁化取向的自由磁性层的磁性隧道结，其磁化取向可在高电阻状态磁化取向和低电阻状态磁化取向之间切换，以及与磁性隧道结电耦合的忆阻体固态元件。 忆阻器具有集成电压与集成电流的器件响应。

公开(公告)号：US08054675B2

公开(公告)日：2011-11-08

申请号：US13028246

申请日：2011-02-16

申请人： Haiwen Xi ,  Hongyue Liu ,  Xiaobin Wang ,  Yong Lu ,  Yiran Chen ,  Yuankai Zheng ,  Dimitar V. Dimitrov ,  Dexin Wang ,  Hai Li

发明人： Haiwen Xi ,  Hongyue Liu ,  Xiaobin Wang ,  Yong Lu ,  Yiran Chen ,  Yuankai Zheng ,  Dimitar V. Dimitrov ,  Dexin Wang ,  Hai Li

IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C11/15

CPC分类号： G11C11/16 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0057

摘要： Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.

摘要翻译： 公开了用于电阻随机存取存储器（RRAM）的可变写和读方法。 这些方法包括初始化写入序列并验证RRAM单元的电阻状态。 如果需要写入脉冲，则通过RRAM单元施加两个或更多写入脉冲，以将期望的数据状态写入RRAM单元。 每个后续写入脉冲具有基本上相同或更大的写入脉冲持续时间。 随后的写入脉冲被施加到RRAM单元，直到RRAM单元处于期望的数据状态，或直到预定数量的写入脉冲已经被施加到RRAM单元为止。 还公开了一种读取方法，其中随后的读取脉冲通过RRAM单元被施加，直到读取成功或直到预定数量的读取脉冲已经被应用于RRAM单元为止。

公开(公告)号：US07944730B2

公开(公告)日：2011-05-17

申请号：US12412546

申请日：2009-03-27

申请人： Yiran Chen ,  Hai Li ,  Wengzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wengzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Hongyue Liu

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

摘要： A method of writing to a resistive sense memory unit includes applying a first voltage across a resistive sense memory cell and a semiconductor transistor to write a first data state to the resistive sense memory cell. The first voltage forms a first write current for a first time duration through the resistive sense memory cell in a first direction. Then the method includes applying a second voltage across the resistive sense memory cell and the transistor to write a second data state to the resistive sense memory cell. The second voltage forms a second write current for a second duration through the resistive sense memory cell in a second direction. The second direction opposes the first direction, the first voltage has a different value than the second voltage, and the first duration is substantially the same as the second duration.

摘要翻译： 写入电阻式读出存储器单元的方法包括在电阻读出存储单元和半导体晶体管两端施加第一电压以将第一数据状态写入电阻读出存储单元。 第一电压在第一方向通过电阻读出存储单元形成第一持续时间的第一写入电流。 然后，该方法包括在电阻读出存储单元和晶体管两端施加第二电压以将第二数据状态写入电阻读出存储单元。 第二电压在第二方向通过电阻读出存储器单元形成第二持续时间的第二写入电流。 第二方向与第一方向相反，第一电压具有与第二电压不同的值，并且第一持续时间基本上与第二持续时间相同。

公开(公告)号：US20110080782A1

公开(公告)日：2011-04-07

申请号：US12967743

申请日：2010-12-14

申请人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

发明人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

IPC分类号： G11C11/15

CPC分类号： G11C8/08 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0071

摘要： Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.

公开(公告)号：US20110029714A1

公开(公告)日：2011-02-03

申请号：US12904653

申请日：2010-10-14

申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

IPC分类号： G06F12/00 ,  G11C11/21 ,  G11C11/16

CPC分类号： G11C8/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

摘要： Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.

摘要翻译： 本发明的各种实施例总体上涉及一种用于在诸如由STRAM或RRAM单元形成的电阻式感测存储器（RSM）阵列上执行部分块更新操作的方法和装置。 RSM阵列被布置成多小区块（扇区），每个块具有物理块地址（PBA）。 第一组用户数据在第一PBA被写入所选择的块。 通过在第二PBA将第二组用户数据写入第二块来执行部分块更新操作，第二组用户数据更新第一PBA中第一组用户数据的一部分。 然后读取第一和第二块以检索第二组用户数据和第一组用户数据的剩余部分。

公开(公告)号：US20110007588A1

公开(公告)日：2011-01-13

申请号：US12502194

申请日：2009-07-13

申请人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

发明人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C15/00

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/025 ,  G11C29/44 ,  G11C29/808 ,  G11C2029/0403

摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.

摘要翻译： 本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。 根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。 测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

公开(公告)号：US07852665B2

公开(公告)日：2010-12-14

申请号：US12406356

申请日：2009-03-18

申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Harry Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Harry Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： G11C7/062 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2207/063

摘要： Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second read current is subsequently applied to the memory cell to generate a second voltage, with the second read current being proportional in magnitude to the first read current. A comparison is made between the first and second voltages to determine the programmed state of the memory cell.

摘要翻译： 本发明的各种实施例通常涉及用于感测诸如自旋扭矩传递随机存取存储器（STRAM）单元的存储器单元的编程状态的方法和装置。 将第一读取电流施加到存储器单元以产生第一电压。 随后将第二读取电流施加到存储器单元以产生第二电压，其中第二读取电流在幅度上与第一读取电流成比例。 在第一和第二电压之间进行比较以确定存储器单元的编程状态。

公开(公告)号：US20100177551A1

公开(公告)日：2010-07-15

申请号：US12352693

申请日：2009-01-13

申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

IPC分类号： G11C11/00 ,  G11C11/416

CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069

摘要： Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.

摘要翻译： 本发明的各种实施例一般涉及一种用于为电阻式感测存储器（RSM）阵列提供不同的比特设置模式的方法和装置，诸如自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM） ）数组。 根据一些实施例，识别非易失性半导体存储器阵列中的一组RSM单元用于位设置操作的应用。 从对RSM单元分别写入的多个位设置值中选择位设置值，以将所述单元置于选择的电阻状态。 所选位设定值此后被写入所识别的组中的RSM单元的至少一部分。

公开(公告)号：US20100110762A1

公开(公告)日：2010-05-06

申请号：US12412546

申请日：2009-03-27

申请人： Yiran Chen ,  Hai Li ,  Wengzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wengzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Hongyue Liu

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

摘要： A method of writing to a resistive sense memory unit includes applying a first voltage across a resistive sense memory cell and a semiconductor transistor to write a first data state to the resistive sense memory cell. The first voltage forms a first write current for a first time duration through the resistive sense memory cell in a first direction. Then the method includes applying a second voltage across the resistive sense memory cell and the transistor to write a second data state to the resistive sense memory cell. The second voltage forms a second write current for a second duration through the resistive sense memory cell in a second direction. The second direction opposes the first direction, the first voltage has a different value than the second voltage, and the first duration is substantially the same as the second duration.

摘要翻译： 写入电阻式读出存储器单元的方法包括在电阻读出存储单元和半导体晶体管两端施加第一电压以将第一数据状态写入电阻读出存储单元。 第一电压在第一方向通过电阻读出存储单元形成第一持续时间的第一写入电流。 然后，该方法包括在电阻读出存储单元和晶体管两端施加第二电压以将第二数据状态写入电阻读出存储单元。 第二电压在第二方向通过电阻读出存储器单元形成第二持续时间的第二写入电流。 第二方向与第一方向相反，第一电压具有与第二电压不同的值，并且第一持续时间基本上与第二持续时间相同。