公开(公告)号：US20140231923A1

公开(公告)日：2014-08-21

申请号：US14346537

申请日：2012-05-16

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/76232 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7846 ,  H01L29/7848

摘要： The present invention provides a semiconductor structure, comprising: a substrate; a gate stack located on the substrate and comprising at least a gate dielectric layer and a gate electrode layer; source/drain regions, located in the substrate on both sides of the gate stack; an STI structure, located in the substrate on both sides of the source/drain regions, wherein the cross-section of the STI structure is trapezoidal, Sigma-shaped or inverted trapezoidal depending on the type of the semiconductor structure. Correspondingly, the present invention further to provides a method of manufacturing the semiconductor structure. In the present invention, STI structures having different shapes can be combined with different stress fillers to apply tensile stress or compressive stress laterally to the channel, which will produce a positive impact on the electron mobility of NMOS and the hole mobility of PMOS and increase the channel current of the device, thereby effectively improving the performance of the semiconductor structure.

摘要翻译： 本发明提供一种半导体结构，包括：基板; 位于所述基板上并且至少包括栅极电介质层和栅极电极层的栅极堆叠; 源极/漏极区域，位于栅极堆叠两侧的衬底中; STI结构，位于源极/漏极区两侧的衬底中，其中根据半导体结构的类型，STI结构的横截面为梯形，Σ形或倒梯形。 相应地，本发明还提供一种制造半导体结构的方法。 在本发明中，具有不同形状的STI结构可以与不同的应力填料组合以向沟道侧向施加拉伸应力或压应力，这将对NMOS的电子迁移率和PMOS的空穴迁移率产生积极影响，并增加 通道电流，从而有效地提高了半导体结构的性能。

公开(公告)号：US20130241004A1

公开(公告)日：2013-09-19

申请号：US13520618

申请日：2012-04-11

申请人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

发明人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L21/8236

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7845

摘要： The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.

摘要翻译： 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层， 第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且 栅极填充层具有第二应力。 形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简单高效地提高器件载流子迁移率，器件性能也是 增强。

公开(公告)号：US20130221535A1

公开(公告)日：2013-08-29

申请号：US13517050

申请日：2012-02-29

申请人： Xiaolong Ma ,  Huaxiang Yin ,  Lichuan Zhao

发明人： Xiaolong Ma ,  Huaxiang Yin ,  Lichuan Zhao

IPC分类号： H01L23/48 ,  B32B9/00 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/30 ,  H01L2924/00

摘要： A diffusion barrier layer, a metal interconnect arrangement and a method of manufacturing the same are disclosed. In one embodiment, the metal interconnect arrangement may comprise a conductive plug/interconnect wire for electrical connection, and a diffusion barrier layer provided on at least a portion of a surface of the conductive plug/interconnect wire. The diffusion barrier layer may comprise insulating amorphous carbon.

摘要翻译： 公开了一种扩散阻挡层，金属互连装置及其制造方法。 在一个实施例中，金属互连装置可以包括用于电连接的导电插头/互连线，以及设置在导电插头/互连线的表面的至少一部分上的扩散阻挡层。 扩散阻挡层可以包括绝缘无定形碳。

公开(公告)号：US08405062B2

公开(公告)日：2013-03-26

申请号：US11713738

申请日：2007-03-05

申请人： Huaxiang Yin ,  Young-soo Park ,  Wenxu Xianyu ,  Hans S. Cho

发明人： Huaxiang Yin ,  Young-soo Park ,  Wenxu Xianyu ,  Hans S. Cho

IPC分类号： H01L47/00

CPC分类号： H01L21/02686 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

摘要： A method of forming a poly-silicon pattern may include forming an amorphous silicon pattern on a lower layer; forming a capping layer on the substrate covering the amorphous silicon pattern; poly-crystallizing the amorphous silicon pattern using an excimer laser annealing process; and removing the capping layer.

摘要翻译： 形成多晶硅图案的方法可以包括在下层上形成非晶硅图案; 在覆盖所述非晶硅图案的所述基板上形成覆盖层; 使用准分子激光退火工艺多晶结晶非晶硅图案; 并去除覆盖层。

公开(公告)号：US08383472B2

公开(公告)日：2013-02-26

申请号：US13067306

申请日：2011-05-24

申请人： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

发明人： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L27/1225 ,  H01L27/1251

摘要： Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.

摘要翻译： 提供逆变器，逆变器的制造方法以及包括逆变器的逻辑电路。 反相器可以包括具有不同沟道层结构的第一晶体管和第二晶体管。 第一晶体管的沟道层可以包括下层和上层，并且第二晶体管的沟道层可以与下层和上层之一相同。 下层和上层中的至少一层可以是氧化物层。 逆变器可以是增强/耗尽型（E / D）型逆变器或互补型逆变器。

公开(公告)号：US08097499B2

公开(公告)日：2012-01-17

申请号：US11702624

申请日：2007-02-06

申请人： Wenxu Xianyu ,  Young-soo Park ,  Jun-ho Lee ,  Hyuk Lim ,  Hans S. Cho ,  Huaxiang Yin

发明人： Wenxu Xianyu ,  Young-soo Park ,  Jun-ho Lee ,  Hyuk Lim ,  Hans S. Cho ,  Huaxiang Yin

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L21/02609 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02516 ,  H01L21/02532

摘要： A semiconductor device and method thereof. The example method may include forming a semiconductor device, including forming a first layer on a substrate, the first layer including aluminum nitride (AlN), forming a second layer by oxidizing a surface of the first layer and forming a third layer on the second layer, the first, second and third layers each being highly oriented with respect to one of a plurality crystallographic planes. The example semiconductor device may include a substrate including a first layer, the first layer including aluminum nitride (AlN), a second layer formed by oxidizing a surface of the first layer and a third layer formed on the second layer, the first, second and third layers each being highly oriented with respect to one of a plurality crystallographic planes.

摘要翻译： 半导体器件及其方法。 示例性方法可以包括形成半导体器件，包括在衬底上形成第一层，第一层包括氮化铝（AlN），通过氧化第一层的表面并在第二层上形成第三层来形成第二层 ，第一层，第二层和第三层各自相对于多个晶面之一高度取向。 示例性半导体器件可以包括：衬底，其包括第一层，第一层包括氮化铝（AlN），通过氧化第一层的表面形成的第二层和形成在第二层上的第三层，第一层，第二层和第二层 第三层各自相对于多个晶面之一高度取向。

公开(公告)号：US07994588B2

公开(公告)日：2011-08-09

申请号：US12073398

申请日：2008-03-05

申请人： Huaxiang Yin ,  Young-soo Park ,  Sun-Il Kim

发明人： Huaxiang Yin ,  Young-soo Park ,  Sun-Il Kim

IPC分类号： H01L21/70

CPC分类号： H01L27/115 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/1203

摘要： Example embodiments provide a nonvolatile memory device that may be integrated through stacking, a stack module, and a method of fabricating the nonvolatile memory device. In the nonvolatile memory device according to example embodiments, at least one bottom gate electrode may be formed on a substrate. At least one charge storage layer may be formed on the at least one bottom gate electrode, and at least one semiconductor channel layer may be formed on the at least one charge storage layer.

摘要翻译： 示例性实施例提供了可以通过堆叠集成的非易失性存储器件，堆叠模块和制造非易失性存储器件的方法。 在根据示例性实施例的非易失性存储器件中，可以在衬底上形成至少一个底栅电极。 至少一个电荷存储层可以形成在至少一个底栅电极上，并且至少一个半导体沟道层可以形成在至少一个电荷存储层上。

公开(公告)号：US07977978B2

公开(公告)日：2011-07-12

申请号：US12591654

申请日：2009-11-25

申请人： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

发明人： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

IPC分类号： H03K19/00

CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L27/1225 ,  H01L27/1251

摘要： Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.

摘要翻译： 提供逆变器，逆变器的制造方法以及包括逆变器的逻辑电路。 反相器可以包括具有不同沟道层结构的第一晶体管和第二晶体管。 第一晶体管的沟道层可以包括下层和上层，并且第二晶体管的沟道层可以与下层和上层之一相同。 下层和上层中的至少一层可以是氧化物层。 逆变器可以是增强/耗尽型（E / D）型逆变器或互补型逆变器。

公开(公告)号：US07816678B2

公开(公告)日：2010-10-19

申请号：US12175778

申请日：2008-07-18

申请人： Takashi Noguchi ,  Wenxu Xianyu ,  Huaxiang Yin

发明人： Takashi Noguchi ,  Wenxu Xianyu ,  Huaxiang Yin

IPC分类号： H01L35/24 ,  H01L51/00 ,  H01L31/00 ,  H01L21/00 ,  H01L51/40

CPC分类号： H01L27/1266 ,  H01L27/1255 ,  H01L27/3244 ,  H01L29/78603

摘要： Provided is an organic light emitting display, in which a semiconductor circuit unit of 2T-1C structure including a switching transistor and a driving transistor formed of single crystalline silicon is formed on a plastic substrate. A method of fabricating the single crystalline silicon includes: growing a single crystalline silicon layer to a predetermined thickness on a crystal growth plate; depositing a buffer layer on the single crystalline silicon layer; forming a partition layer at a predetermined depth in the single crystalline silicon layer by, e.g., implanting hydrogen ions in the single crystalline silicon layer from an upper portion of an insulating layer; attaching a substrate to the buffer layer; and releasing the partition layer of the single crystalline silicon layer by heating the partition layer from the crystal growth plate to obtain a single crystalline silicon layer of a predetermined thickness on the substrate.

摘要翻译： 提供一种有机发光显示器，其中在塑料基板上形成包括开关晶体管和由单晶硅形成的驱动晶体管的2T-1C结构的半导体电路单元。 制造单晶硅的方法包括：在晶体生长板上生长单晶硅层至预定厚度; 在单晶硅层上沉积缓冲层; 通过例如从绝缘层的上部注入单晶硅层中的氢离子，在单晶硅层中形成预定深度的分隔层; 将衬底附接到缓冲层; 以及通过从晶体生长板加热分隔层来释放单晶硅层的分隔层，以在基板上获得预定厚度的单晶硅层。

公开(公告)号：US07772711B2

公开(公告)日：2010-08-10

申请号：US11430117

申请日：2006-05-09

申请人： Takashi Noguchi ,  Hans S. Cho ,  Wenxu Xianyu ,  Do-young Kim ,  Jang-yeong Kwon ,  Huaxiang Yin ,  Kyung-bae Park ,  Xiaoxin Zhang

发明人： Takashi Noguchi ,  Hans S. Cho ,  Wenxu Xianyu ,  Do-young Kim ,  Jang-yeong Kwon ,  Huaxiang Yin ,  Kyung-bae Park ,  Xiaoxin Zhang

IPC分类号： H01L27/11

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  Y10S257/903

摘要： A semiconductor device including a substrate, a P-MOS single crystal TFT formed on the substrate, and an N-MOS single crystal TFT formed on the P-MOS single crystal TFT. The source region of the P-MOS single crystal TFT and the source region of the N-MOS single crystal TFT may be connected to each other. The P-MOS single crystal TFT and the N-MOS single crystal TFT may share a common gate. Also, the P-MOS single crystal TFT may include a single crystal silicon layer with a crystal plane of (100) and a crystal direction of . The N-MOS single crystal TFT may include a single crystal silicon layer having the same crystal direction as the single crystal silicon layer of the P-MOS single crystal TFT and having a tensile stress greater than the single crystal silicon layer of the P-MOS single crystal TFT.

摘要翻译： 包括基板，形成在基板上的P-MOS单晶TFT的半导体器件和形成在P-MOS单晶TFT上的N-MOS单晶TFT。 P-MOS单晶TFT的源极区域和N-MOS单晶TFT的源极区域可以彼此连接。 P-MOS单晶TFT和N-MOS单晶TFT可以共用公共栅极。 此外，P-MOS单晶TFT可以包括具有（100）的晶面并且晶体方向<100的单晶硅层。 N-MOS单晶TFT可以包括与P-MOS单晶TFT的单晶硅层相同的晶体方向的单晶硅层，其拉应力大于P-MOS的单晶硅层 单晶TFT。