公开(公告)号：US08383472B2

公开(公告)日：2013-02-26

申请号：US13067306

申请日：2011-05-24

申请人： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

发明人： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L27/1225 ,  H01L27/1251

摘要： Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.

摘要翻译： 提供逆变器，逆变器的制造方法以及包括逆变器的逻辑电路。 反相器可以包括具有不同沟道层结构的第一晶体管和第二晶体管。 第一晶体管的沟道层可以包括下层和上层，并且第二晶体管的沟道层可以与下层和上层之一相同。 下层和上层中的至少一层可以是氧化物层。 逆变器可以是增强/耗尽型（E / D）型逆变器或互补型逆变器。

公开(公告)号：US07977978B2

公开(公告)日：2011-07-12

申请号：US12591654

申请日：2009-11-25

申请人： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

发明人： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

IPC分类号： H03K19/00

CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L27/1225 ,  H01L27/1251

摘要： Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.

摘要翻译： 提供逆变器，逆变器的制造方法以及包括逆变器的逻辑电路。 反相器可以包括具有不同沟道层结构的第一晶体管和第二晶体管。 第一晶体管的沟道层可以包括下层和上层，并且第二晶体管的沟道层可以与下层和上层之一相同。 下层和上层中的至少一层可以是氧化物层。 逆变器可以是增强/耗尽型（E / D）型逆变器或互补型逆变器。

公开(公告)号：US20110230021A1

公开(公告)日：2011-09-22

申请号：US13067306

申请日：2011-05-24

申请人： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

发明人： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L27/1225 ,  H01L27/1251

摘要： Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.

公开(公告)号：US20100264956A1

公开(公告)日：2010-10-21

申请号：US12591654

申请日：2009-11-25

申请人： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

发明人： Huaxiang Yin ,  I-hun Song ,  Chang-jung Kim ,  Sang-wook Kim ,  Sun-il Kim

IPC分类号： H03K19/20 ,  H01L21/70 ,  H01L27/088

CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L27/1225 ,  H01L27/1251

摘要： Provided are an inverter, a method of manufacturing the inverter, and a logic circuit including the inverter. The inverter may include a first transistor and a second transistor having different channel layer structures. A channel layer of the first transistor may include a lower layer and an upper layer, and a channel layer of the second transistor may be the same as one of the lower layer and the upper layer. At least one of the lower layer and the upper layer may be an oxide layer. The inverter may be an enhancement/depletion (E/D) mode inverter or a complementary inverter.

摘要翻译： 提供逆变器，逆变器的制造方法以及包括逆变器的逻辑电路。 反相器可以包括具有不同沟道层结构的第一晶体管和第二晶体管。 第一晶体管的沟道层可以包括下层和上层，并且第二晶体管的沟道层可以与下层和上层之一相同。 下层和上层中的至少一层可以是氧化物层。 逆变器可以是增强/耗尽型（E / D）型逆变器或互补型逆变器。

公开(公告)号：US20090057745A1

公开(公告)日：2009-03-05

申请号：US12073398

申请日：2008-03-05

申请人： Huaxiang Yin ,  Young-soo Park ,  Sun-Il Kim

发明人： Huaxiang Yin ,  Young-soo Park ,  Sun-Il Kim

IPC分类号： H01L29/788 ,  H01L29/792 ,  H01L21/335

CPC分类号： H01L27/115 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/1203

摘要： Example embodiments provide a nonvolatile memory device that may be integrated through stacking, a stack module, and a method of fabricating the nonvolatile memory device. In the nonvolatile memory device according to example embodiments, at least one bottom gate electrode may be formed on a substrate. At least one charge storage layer may be formed on the at least one bottom gate electrode, and at least one semiconductor channel layer may be formed on the at least one charge storage layer.

摘要翻译： 示例性实施例提供了可以通过堆叠集成的非易失性存储器件，堆叠模块和制造非易失性存储器件的方法。 在根据示例性实施例的非易失性存储器件中，可以在衬底上形成至少一个底栅电极。 至少一个电荷存储层可以形成在至少一个底栅电极上，并且至少一个半导体沟道层可以形成在至少一个电荷存储层上。

公开(公告)号：US07994588B2

公开(公告)日：2011-08-09

申请号：US12073398

申请日：2008-03-05

申请人： Huaxiang Yin ,  Young-soo Park ,  Sun-Il Kim

发明人： Huaxiang Yin ,  Young-soo Park ,  Sun-Il Kim

IPC分类号： H01L21/70

CPC分类号： H01L27/115 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/1203

摘要： Example embodiments provide a nonvolatile memory device that may be integrated through stacking, a stack module, and a method of fabricating the nonvolatile memory device. In the nonvolatile memory device according to example embodiments, at least one bottom gate electrode may be formed on a substrate. At least one charge storage layer may be formed on the at least one bottom gate electrode, and at least one semiconductor channel layer may be formed on the at least one charge storage layer.

摘要翻译： 示例性实施例提供了可以通过堆叠集成的非易失性存储器件，堆叠模块和制造非易失性存储器件的方法。 在根据示例性实施例的非易失性存储器件中，可以在衬底上形成至少一个底栅电极。 至少一个电荷存储层可以形成在至少一个底栅电极上，并且至少一个半导体沟道层可以形成在至少一个电荷存储层上。

公开(公告)号：US09281398B2

公开(公告)日：2016-03-08

申请号：US14355664

申请日：2012-07-03

申请人： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/7848 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/66636 ,  H01L29/7834

摘要： The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

摘要翻译： 本发明公开了一种半导体器件，其包括衬底，衬底上的栅极堆叠结构，栅极堆叠结构下的衬底中的沟道区，以及沟道区两侧的源极和漏极区，其中存在 在形成源极和漏极区的沟道区的下侧和两侧具有应力层。 根据本发明的半导体器件及其制造方法，在由硅系材料制成的沟道区域的两侧和下方形成应力层，以作用于沟道区域，从而有效地增加 通道区域的载波移动性和设备性能的提高。

公开(公告)号：US20150102416A1

公开(公告)日：2015-04-16

申请号：US14396845

申请日：2012-05-17

申请人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L21/8234 ,  H01L29/51 ,  H01L27/092

CPC分类号： H01L21/28088 ,  H01L21/28 ,  H01L21/28008 ,  H01L21/28026 ,  H01L21/28044 ,  H01L21/28079 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/517 ,  H01L29/66515 ,  H01L29/66545

摘要： A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type work function metal diffusion source layer in the first gate trench and the second gate trench; forming a heat isolation layer that shields the region of the first type device; and thermally annealing the regions where the first type device and the second type device are located.

摘要翻译： 一种用于制造双金属CMOS器件的方法，包括：在所述第一栅极沟槽和所述第二栅极沟槽中形成第一类型金属功函数调制层; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二类型功函数金属扩散源层; 形成屏蔽所述第一类型装置的区域的热隔离层; 并对第一类型器件和第二类型器件所在的区域进行热退火。

公开(公告)号：US08994119B2

公开(公告)日：2015-03-31

申请号：US13520618

申请日：2012-04-11

申请人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

发明人： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC分类号： H01L27/088 ,  H01L21/8236 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7845

摘要： The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.

摘要翻译： 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层， 第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且 栅极填充层具有第二应力。 形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简化高效地提高器件载流子迁移率，器件性能也 增强。

公开(公告)号：US08816326B2

公开(公告)日：2014-08-26

申请号：US13497249

申请日：2011-11-25

申请人： Huaxiang Yin ,  Jun Luo ,  Chao Zhao ,  Honggang Liu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Jun Luo ,  Chao Zhao ,  Honggang Liu ,  Dapeng Chen

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L29/08

CPC分类号： H01L29/66462 ,  H01L29/0895 ,  H01L29/7391 ,  H01L29/7785 ,  Y10S977/938

摘要： A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.

摘要翻译： 一种半导体器件，包括：半导体衬底; 半导体衬底上的沟道区，所述沟道区包括量子阱结构; 在沟道区域的侧面上的源极区域和漏极区域; 通道区域上的栅极结构; 其中用于沟道区，源区和漏区的材料具有不同的能带，并且在源极区域和沟道区域之间存在隧道势垒结构。