公开(公告)号：US06610142B1

公开(公告)日：2003-08-26

申请号：US08977944

申请日：1997-11-24

申请人： Toru Takayama ,  Hongyong Zhang ,  Shunpei Yamazaki ,  Yasuhiko Takemura

发明人： Toru Takayama ,  Hongyong Zhang ,  Shunpei Yamazaki ,  Yasuhiko Takemura

IPC分类号： C30B1322

CPC分类号： H01L27/12 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02672 ,  H01L21/02675 ,  H01L27/1277 ,  H01L27/1285 ,  H01L29/66757 ,  H01L29/78654 ,  H01L29/78675

摘要： A process for fabricating a semiconductor at a lower crystallization temperature and yet at a shorter period of time, which comprises forming an insulator coating on a substrate; exposing said insulator coating to a plasma; forming an amorphous silicon film on said insulator coating after its exposure to said plasma; and heat treating said silicon film in the temperature range of from 400 to 650° C. or at a temperature not higher than the glass transition temperature of the substrate. The nucleation sites are controlled by selectively exposing the amorphous silicon film to a plasma or by selectively applying a substance containing elements having a catalytic effect thereto. A process for fabricating a thin film transistor using the same is also disclosed.

摘要翻译： 一种制造半导体的方法，该半导体在较低的结晶温度下并且在较短的时间内，其包括在基片上形成绝缘体涂层; 将所述绝缘体涂层暴露于等离子体; 在暴露于所述等离子体之后，在所述绝缘体涂层上形成非晶硅膜; 在400〜650℃的温度范围内或在不高于基板的玻璃化转变温度的温度下对所述硅膜进行热处理。 通过选择性地将非晶硅膜暴露于等离子体或通过选择性地施加含有其催化作用的元素的物质来控制成核位点。 还公开了使用其制造薄膜晶体管的工艺。

公开(公告)号：US06528852B2

公开(公告)日：2003-03-04

申请号：US09983366

申请日：2001-10-24

申请人： Yasuhiko Takemura

发明人： Yasuhiko Takemura

IPC分类号： H01L2701

CPC分类号： H01L27/124 ,  H01L29/41733 ,  H01L29/66757 ,  H01L29/78645 ,  H01L29/78648

摘要： In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side gate electrode connected to a static potential, the bottom side gate electrode being provided between the active layer and a substrate. The bottom side gate electrode may be electrically connected to only one of a source and a drain of the field effect type device. Also, the production methods therefor are disclosed.

摘要翻译： 在具有薄膜状有源层的场效应器件中，提供了一种薄膜状半导体器件，其包括在有源层上的顶侧栅电极和连接到静电势的底侧栅电极，底侧 栅电极设置在有源层和衬底之间。 底侧栅电极可以仅电场连接到场效应型装置的源极和漏极中的一个。 另外，公开了其制造方法。

公开(公告)号：US06475837B2

公开(公告)日：2002-11-05

申请号：US09850886

申请日：2001-05-07

申请人： Hongyong Zhang ,  Naoaki Yamaguchi ,  Yasuhiko Takemura

发明人： Hongyong Zhang ,  Naoaki Yamaguchi ,  Yasuhiko Takemura

IPC分类号： H01L2100

CPC分类号： G02F1/136286 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2201/121 ,  G02F2201/40

摘要： An auxiliary capacitor for a pixel of an active matrix type liquid crystal display is provided without decreasing the aperture ratio. A transparent conductive film for a common electrode is formed under a pixel electrode constituted by a transparent conductive film with an insulation film provided therebetween. Further, the transparent conductive film for the common electrode is maintained at fixed potential, formed so as to cover a gate bus line and a source bus line, and configured such that signals on each bus line are not applied to the pixel electrode. The pixel electrode is disposed so that all edges thereof overlap the gate bus line and source bus line. As a result, each of the bus lines serves as a black matrix. Further, the pixel electrode overlaps the transparent conductive film for the common electrode to form a storage capacitor.

摘要翻译： 提供一种用于有源矩阵型液晶显示器的像素的辅助电容器，而不会降低开口率。 用于公共电极的透明导电膜形成在由透明导电膜构成的像素电极之下，其间设置有绝缘膜。 此外，用于公共电极的透明导电膜保持固定电位，形成为覆盖栅极总线和源极总线，并且被配置为使得每个总线上的信号不被施加到像素电极。 像素电极被设置成使得其所有边缘与栅极总线和源极总线重叠。 结果，每条总线作为黑矩阵。 此外，像素电极与用于公共电极的透明导电膜重叠形成存储电容器。

公开(公告)号：US06423586B1

公开(公告)日：2002-07-23

申请号：US09038926

申请日：1998-03-09

申请人： Shunpei Yamazaki ,  Hongyong Zhang ,  Naoto Kusumoto ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Hongyong Zhang ,  Naoto Kusumoto ,  Yasuhiko Takemura

IPC分类号： H01L21336

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/2026 ,  H01L31/208 ,  Y02E10/50 ,  Y02P70/521 ,  Y10T29/41

摘要： A semiconductor material and a method for forming the same, said semiconductor material having produced by a process comprising melting a noncrystal semiconductor film containing therein carbon, nitrogen, and oxygen each at a concentration of 5×1019 atoms·cm−3 or lower, preferably 1×1019 atoms·cm−3 or lower, by irradiating a laser beam or a high intensity light equivalent to a laser beam to said noncrystal semiconductor film, and then recrystallizing the thus molten amorphous silicon film. The present invention provides thin film semiconductors having high mobility at an excellent reproducibility, said semiconductor materials being useful for fabricating thin film semiconductor devices such as thin film transistors improved in device characteristics.

摘要翻译： 一种半导体材料及其形成方法，所述半导体材料通过以下方法制备，所述方法包括以5×10 19原子/ cm 3以下，优选1×1019原子的浓度熔化含有碳，氮和氧的非晶半导体膜 cm-3以下，通过将激光等离子体的激光或高强度光照射到所述非晶半导体膜，然后使这样熔融的非晶硅膜重结晶。 本发明提供具有优异的再现性的高迁移率的薄膜半导体，所述半导体材料可用于制造薄膜晶体管，例如改善器件特性的薄膜晶体管。

公开(公告)号：US06355512B1

公开(公告)日：2002-03-12

申请号：US09545854

申请日：2000-04-10

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura

IPC分类号： H01L2100

CPC分类号： H01L29/66757 ,  H01L29/458

摘要： In producing a top gate type or a bottom gate type thin film transistor (TFT), after a metal film for forming silicide is formed on a semiconductor active layer provided on an insulating surface, an N-type or P-type impurity ion is introduced into the semiconductor active layer using an anodizable gate electrode and an anodic oxide formed on the surface of the gate electrode as masks. The exposing portion of the semiconductor active layer is reacted with the metal film, so that a silicide layer is formed in the portion. Then, non-reacted portion of the metal film is removed.

摘要翻译： 在制造顶栅型或底栅型薄膜晶体管（TFT）时，在设置在绝缘表面上的半导体有源层上形成用于形成硅化物的金属膜之后，引入N型或P型杂质离子 使用形成在栅电极的表面上的阳极化电极和阳极氧化物作为掩模，进入半导体有源层。 半导体活性层的曝光部分与金属膜反应，从而在该部分中形成硅化物层。 然后，除去金属膜的未反应部分。

公开(公告)号：US06340830B1

公开(公告)日：2002-01-22

申请号：US09237854

申请日：1999-01-27

申请人： Yasuhiko Takemura

发明人： Yasuhiko Takemura

IPC分类号： H01L2701

CPC分类号： H01L27/124 ,  H01L29/41733 ,  H01L29/66757 ,  H01L29/78645 ,  H01L29/78648

摘要： In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side gate electrode connected to a static potential, the bottom side gate electrode being provided between the active layer and a substrate. The bottom side gate electrode may be electrically connected to only one of a source and a drain of the field effect type device. Also, the production methods therefor are disclosed.

摘要翻译： 在具有薄膜状有源层的场效应器件中，提供了一种薄膜状半导体器件，其包括在有源层上的顶侧栅电极和连接到静电势的底侧栅电极，底侧 栅电极设置在有源层和衬底之间。 底侧栅电极可以仅电场连接到场效应型装置的源极和漏极中的一个。 另外，公开了其制造方法。

公开(公告)号：US06337731B1

公开(公告)日：2002-01-08

申请号：US09419619

申请日：1999-10-15

申请人： Yasuhiko Takemura

发明人： Yasuhiko Takemura

IPC分类号： G02F1136

CPC分类号： G02F1/136213 ,  G02F1/134309 ,  G09G3/3648 ,  G09G3/3659 ,  G09G2320/0209 ,  G09G2320/0219

摘要： An active matrix display device for suppressing voltage variation &Dgr;V due to off-operation of a gate pulse, including TFTs and picture-element electrodes, at least one of the TFTs being assigned to each picture element, and each of the TFTs having a gate electrode connected to a gate line (first gate line), and a source and a drain one of which is connected to a data line, wherein a picture-element electrode concerned is formed so as to be overlapped with the first gate line through an insulator, and also so as to be overlapped through an insulator with a gate line other than the first gate line or a wiring disposed in parallel to the first gate line.

摘要翻译： 一种有源矩阵显示装置，用于抑制由于包括TFT和像素电极的栅极脉冲的断开而导致的电压变化DELTAV，至少一个TFT被分配给每个像素，并且每个TFT具有栅电极 连接到栅极线（第一栅极线），并且其源极和漏极连接到数据线，其中相关的像素电极形成为通过绝缘体与第一栅极线重叠， 并且还通过具有除了第一栅极线之外的栅极线或与第一栅极线平行设置的布线的绝缘体重叠。

公开(公告)号：US06262438B1

公开(公告)日：2001-07-17

申请号：US08962047

申请日：1997-10-31

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura

IPC分类号： H01L2904

CPC分类号： H01L29/78636 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136227 ,  H01L27/1255 ,  H01L29/78633

摘要： An active matrix circuit using top-gate type thin-film transistors is characterized in that an auxiliary capacitor is formed between a black matrix and an N-type or P-type active layer, and uses, as a dielectric, a silicon nitride layer used as a passivation film of an interlayer insulator. Also, an active matrix circuit using bottom-gate type thin-film transistors is characterized in that two auxiliary capacitors. One of the auxiliary capacitors is formed between a capacitor wiring line formed on a substrate and an N-type or P-type conductive region or a metal wiring line connected to the conductive region, and uses a gate insulating film as a dielectric. The other one of the auxiliary capacitors is formed between a black matrix and said N-type or P-type conductive region or said metal wiring line connected to the conductive region, and uses a silicon nitride layer used as a passivation film as a dielectric. Said two auxiliary capacitors are located in three-dimension for preventing aperture ratio from lowering.

摘要翻译： 使用顶栅型薄膜晶体管的有源矩阵电路的特征在于，在黑矩阵和N型或P型有源层之间形成辅助电容器，并且使用用作电介质的氮化硅层 作为层间绝缘体的钝化膜。 而且，使用底栅型薄膜晶体管的有源矩阵电路的特征在于两个辅助电容器。 辅助电容器中的一个形成在形成在基板上的电容布线与N型或P型导电区域或连接到导电区域的金属布线之间，并且使用栅极绝缘膜作为电介质。 辅助电容器中的另一个形成在黑矩阵和连接到导电区域的所述N型或P型导电区域或所述金属布线之间，并且使用用作钝化膜的氮化硅层作为电介质。 所述两个辅助电容器位于三维中以防止开口率降低。

公开(公告)号：US06259120B1

公开(公告)日：2001-07-10

申请号：US09224955

申请日：1999-01-04

申请人： Hongyong Zhang ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Yasuhiko Takemura

发明人： Hongyong Zhang ,  Hideto Ohnuma ,  Naoaki Yamaguchi ,  Yasuhiko Takemura

IPC分类号： H01L2904

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78618

摘要： In a thin film transistor (TFT), a mask is formed on a gate electrode, and a porous anodic oxide is formed in both sides of the gate electrode using a relatively low voltage. A barrier anodic oxide is formed between the gate electrode and the porous anodic oxide and on the gate electrode using a relatively high voltage. A gate insulating film is etched using the barrier anodic oxide as a mask. The porous anodic oxide is selectively etched after etching barrier anodic oxide, to obtain a region of an active layer on which the gate insulating film is formed and the other region of the active layer on which the gate insulating film is not formed. An element including at least one of oxygen, nitrogen and carbon is introduced into the region of the active layer at high concentration in comparison with a concentration of the other region of the active layer. Further, N- or P-type impurity is introduced into the active layer. Accordingly, high resistance impurity regions are formed in both sides of a channel forming region.

摘要翻译： 在薄膜晶体管（TFT）中，在栅电极上形成掩模，并且使用相对低的电压在栅电极的两侧形成多孔阳极氧化物。 在栅电极和多孔阳极氧化物之间以及使用较高电压的栅电极上形成阻挡阳极氧化物。 使用阻挡阳极氧化物作为掩模蚀刻栅极绝缘膜。 在蚀刻阻挡阳极氧化物之后，选择性地蚀刻多孔阳极氧化物，以获得其上形成有栅极绝缘膜的有源层的区域和不形成栅极绝缘膜的有源层的另一区域。 与活性层的其他区域的浓度相比，包含氧，氮和碳中的至少一种的元素以高浓度被引入活性层的区域。 此外，将N型或P型杂质引入有源层。 因此，在沟道形成区域的两侧形成高电阻杂质区域。

公开(公告)号：US06218678B1

公开(公告)日：2001-04-17

申请号：US08815070

申请日：1997-03-11

申请人： Hongyong Zhang ,  Naoaki Yamaguchi ,  Yasuhiko Takemura

发明人： Hongyong Zhang ,  Naoaki Yamaguchi ,  Yasuhiko Takemura

IPC分类号： H01L2904

CPC分类号： H01L27/1251 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621

摘要： A method of manufacturing a semiconductor device comprises the steps of forming a first insulating film on a semiconductor layer, forming a gate electrode on the insulating film, pattering the first insulating film into a second insulating film so that a portion of the semiconductor layer is exposed while the second insulating film has extensions which extend beyond the side edges of the gate electrode, and performing ion introduction for forming impurity regions using the gate electrode and extensions of the gate insulating film as a mask. The condition of the ion introduction is varied in order to control the regions of the semiconductor layer to be added with the impurity and the concentration of the impurity therein.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体层上形成第一绝缘膜，在绝缘膜上形成栅电极，将第一绝缘膜图案化为第二绝缘膜，以使半导体层的一部分露出 而第二绝缘膜具有延伸超过栅电极的侧边缘的延伸，并且使用栅极电极和栅极绝缘膜的延伸作为掩模来执行用于形成杂质区域的离子引入。 离子引入的条件是变化的，以便控制加入杂质的半导体层的区域和其中杂质的浓度。