公开(公告)号：US5847595A

公开(公告)日：1998-12-08

申请号：US757861

申请日：1996-11-27

申请人： Takashi Kono ,  Tsukasa Ooishi ,  Hideto Hidaka

发明人： Takashi Kono ,  Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G01R31/28 ,  G06F11/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C29/00 ,  G11C29/12 ,  G11C29/14 ,  H03K3/01

CPC分类号： G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/48 ,  G01R31/31721

摘要： A semiconductor memory device includes a mode detection circuit for generating a mode detection signal in response to external input signals /RAS, /CAS and /WE, an internal potential generating circuit for generating and supplying to an output node an internal potential, in response to an activated potential control signal, and an internal potential control circuit for activating a potential control signal when a potential at the output node has not yet reached a predetermined potential in a case where mode detection signal indicates a mode other than the test mode, and for activating the potential control signal when the potential at the output node has not yet reached an externally supplied external reference potential in a case where the mode detection signal indicates the test mode. When external input signals are applied at a predetermined timing, a mode detection signal indicating the test mode is generated, and when the potential at the output node of the internal potential generating circuit has not yet reached the external reference potential, an internal potential is generated and supplied to the output node. Therefore, the internal potential can be controlled in accordance with the external reference potential.

摘要翻译： 半导体存储器件包括：模式检测电路，用于响应于外部输入信号/ RAS，/ CAS和/ WE生成模式检测信号;内部电位产生电路，用于响应于 激活电位控制信号和内部电位控制电路，用于在模式检测信号表示除了测试模式之外的模式的情况下当输出节点的电位尚未达到预定电位时激活电位控制信号，并且 在模式检测信号表示测试模式的情况下，当输出节点的电位尚未达到外部提供的外部参考电位时，激活电位控制信号。 当在预定定时施加外部输入信号时，产生指示测试模式的模式检测信号，并且当内部电位发生电路的输出节点处的电位尚未达到外部参考电位时，产生内部电位 并提供给输出节点。 因此，可以根据外部参考电位来控制内部电位。

公开(公告)号：US5793686A

公开(公告)日：1998-08-11

申请号：US755930

申请日：1996-11-25

申请人： Kiyohiro Furutani ,  Tsukasa Ooishi ,  Mikio Asakura ,  Hideto Hidaka ,  Kei Hamade ,  Yoshito Nakaoka

发明人： Kiyohiro Furutani ,  Tsukasa Ooishi ,  Mikio Asakura ,  Hideto Hidaka ,  Kei Hamade ,  Yoshito Nakaoka

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C29/00 ,  G11C29/14 ,  G11C29/34 ,  G11C29/38 ,  G11C7/00

CPC分类号： G11C29/38 ,  G11C29/34 ,  G11C7/1051 ,  G11C7/1078

摘要： Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

公开(公告)号：USRE36842E

公开(公告)日：2000-08-29

申请号：US70016

申请日：1998-04-30

申请人： Kazutami Arimoto ,  Shigeki Tomishima ,  Hideto Hidaka

发明人： Kazutami Arimoto ,  Shigeki Tomishima ,  Hideto Hidaka

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C29/80 ,  G11C11/4085 ,  G11C29/83 ,  G11C29/84

摘要： A memory array MA.sub.0 is divided into four sub memory arrays by sense amplifier strips. Word drivers belonging to each sub memory array are connected to a corresponding segment boosted signal line. A fuse is connected to each segment boosted signal line. By blowing out a fuse, the sub memory array corresponding to the blown out fuse is no longer used. The sub memory array that is no longer used is exchanged with a spare sub memory array of a spare memory array.

摘要翻译： 存储器阵列MA0由读出放大器条分成四个子存储器阵列。 属于每个子存储器阵列的字驱动器连接到对应的段升压信号线。 保险丝连接到每个段升压信号线。 通过吹出保险丝，不再使用对应于熔断器的子存储器阵列。 不再使用的子存储器阵列与备用存储器阵列的备用子存储器阵列交换。

公开(公告)号：US5815454A

公开(公告)日：1998-09-29

申请号：US831788

申请日：1997-04-09

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C5/00

CPC分类号： G11C7/06 ,  G11C5/14

摘要： A semiconductor memory device includes a sense amp band including a plurality of sense amplifiers, and a plurality of operation power supply potential lines and a plurality of ground potential lines arranged in a meshed shape. The operation power supply potential lines and the ground potential lines include the lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to an operation power supply potential line and a ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. The drive component is provided one for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of operation power supply potential lines and the plurality of ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potentials is generated to allow a stable supply of a power supply potential and a ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to a proximate operation power supply potential line and ground line through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.

摘要翻译： 半导体存储器件包括包括多个读出放大器的检测放大器带，以及以网状形状布置的多个操作电源电位线和多个接地电位线。 操作电源电位线和接地电位线包括与感测放大器频带平行并且接近的线。 感测放大器频带中的每个读出放大器通过驱动部件连接到操作电源电位线和布置在感测放大器附近并与之并联的接地线。 驱动部件被设置用于预定数量的读出放大器，并且响应于来自与感测放大器频带平行布置的信号线的读出放大器激活信号而被导通。 多个操作电源电位线和布置成网状的多个接地线在交叉点处接触。 因此，在半导体存储装置中，不产生电源电位的分配，能够稳定地供给任意的电路部分的电源电位和接地电位。 此外，由于读出放大器通过驱动部件连接到邻近的操作电源电位线和接地线，所以可靠且高速的感测操作是可能的，而与感测放大器驱动信号线的长度无关。

公开(公告)号：US5724293A

公开(公告)日：1998-03-03

申请号：US816102

申请日：1997-03-14

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C5/14

摘要： A semiconductor memory device includes a sense amp band including a plurality of sense amplifiers, and a plurality of operation power supply potential lines and a plurality of ground potential lines arranged in a meshed shape. The operation power supply potential lines and the ground potential lines include the lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to an operation power supply potential line and a ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. The drive component is provided one for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of operation power supply potential lines and the plurality of ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potentials is generated to allow a stable supply of a power supply potential and a ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to a proximate operation power supply potential line and ground line through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.

公开(公告)号：US5650972A

公开(公告)日：1997-07-22

申请号：US692819

申请日：1996-07-29

申请人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

发明人： Shigeki Tomishima ,  Mikio Asakura ,  Kazutami Arimoto ,  Hideto Hidaka

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C5/14

摘要： A semiconductor memory device includes a sense amp band including a plurality of sense amplifiers, and a plurality of operation power supply potential lines and a plurality of ground potential lines arranged in a meshed shape. The operation power supply potential lines and the ground potential lines include the lines arranged in parallel with and in proximity to the sense amp band. Each sense amplifier in the sense amp band is connected to an operation power supply potential line and a ground line arranged in proximity to and in parallel with the sense amplifier through a drive component. The drive component is provided one for a predetermined number of sense amplifiers, and is rendered conductive in response to a sense amplifier activation signal from a signal line arranged in parallel with the sense amp band. The plurality of operation power supply potential lines and the plurality of ground lines arranged in a meshed shape are contacted at crossings. Therefore, in the semiconductor memory device, no distribution of power supply potentials is generated to allow a stable supply of a power supply potential and a ground potential to an arbitrary circuit portion. In addition, since a sense amplifier is connected to a proximate operation power supply potential line and ground line through a drive component, a reliable and high-speed sensing operation is possible irrespective of a length of a sense amp drive signal line.

公开(公告)号：US5604707A

公开(公告)日：1997-02-18

申请号：US466049

申请日：1995-06-06

申请人： Shigehiro Kuge ,  Shigeki Tomishima ,  Kazutami Arimoto ,  Hideto Hidaka ,  Takahiro Tsuruda

发明人： Shigehiro Kuge ,  Shigeki Tomishima ,  Kazutami Arimoto ,  Hideto Hidaka ,  Takahiro Tsuruda

IPC分类号： G11C11/401 ,  G11C5/14 ,  G11C11/403 ,  G11C11/404 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C5/146 ,  G11C11/4074

摘要： A semiconductor memory device includes a semiconductor substrate, a plurality of memory blocks, first and second substrate potential generating circuits and a select circuit. The semiconductor substrate includes a plurality of wells corresponding to the memory blocks. Each memory block includes a plurality of memory cells formed on corresponding wells. The select circuit supplies to the well of the activated memory block a deep substrate potential generated by the first substrate potential generating circuit, and supplies to the well of the unselected memory block a shallow substrate potential generated by the second substrate potential generating circuit. Thereby, the minimum operation in the inactive memory block is ensured in spite of the fact that a power consumption of the inactive memory block is reduced.

摘要翻译： 半导体存储器件包括半导体衬底，多个存储器块，第一和第二衬底电位产生电路以及选择电路。 半导体衬底包括对应于存储块的多个阱。 每个存储块包括形成在相应的阱上的多个存储单元。 所述选择电路向所述激活的存储器的阱提供阻挡由所述第一衬底电位产生电路产生的深衬底电位，并且向所述未选择的存储器块的阱提供由所述第二衬底电位产生电路产生的浅衬底电位。 因此，尽管非活动存储器块的功耗被降低，但确保了非活动存储器块中的最小操作。

公开(公告)号：US20050128800A1

公开(公告)日：2005-06-16

申请号：US11045100

申请日：2005-01-31

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/56

CPC分类号： G11C7/1051 ,  G11C7/06 ,  G11C11/16 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028

摘要： In read operation, a current from a current supply transistor flows through a selected memory cell and a data line. Moreover, a bias magnetic field having such a level that does not destroy storage data is applied to the selected memory cell. By application of the bias magnetic field, an electric resistance of the selected memory cell changes in the positive or negative direction depending on the storage data level. A sense amplifier amplifies the difference between voltages on the data line before and after the change in electric resistance of the selected memory cell. Data is thus read from the selected memory cell by merely accessing the selected memory cell. Moreover, since the data line and the sense amplifier are insulated from each other by a capacitor, the sense amplifier can be operated in an optimal input voltage range regardless of magnetization characteristics of the memory cells.

摘要翻译： 在读取操作中，来自电流供给晶体管的电流流过选定的存储单元和数据线。 此外，具有不破坏存储数据的等级的偏置磁场被施加到所选存储单元。 通过施加偏置磁场，所选择的存储单元的电阻根据存储数据电平在正或负方向上变化。 读出放大器放大所选存储单元的电阻变化前后的数据线上的电压差。 因此，通过仅访问所选择的存储器单元，从所选择的存储器单元读取数据。 此外，由于数据线和读出放大器通过电容器彼此绝缘，所以无论存储器单元的磁化特性如何，读出放大器都可以在最佳输入电压范围内工作。

公开(公告)号：US06690241B2

公开(公告)日：2004-02-10

申请号：US09539892

申请日：2000-03-31

申请人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

发明人： Tsukasa Ooishi ,  Tomoya Kawagoe ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： H03B502

CPC分类号： G11C29/028 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/50 ,  G11C29/50012

摘要： A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied. The internal timer includes an oscillator formed of a plurality of inverters connected in ring shape and a variable capacitance circuit for each inverter. Each variable capacitance circuit includes a plurality of sets of transfer gates, fuses and capacitors connected between the output node of the corresponding inverter and a prescribed potential line.

摘要翻译： 测试器连接到设置在DRAM芯片中的信号输出端子，并且监视从内部定时器输出的时钟信号的频率。 通过改变3位信号的组合来改变时钟信号的频率，以获得最接近设定值的频率的信号。 内部定时器中的保险丝断开以设置时钟信号的频率，以获得与施加该信号的情况相同的状态。 内部定时器包括由环形连接的多个逆变器和每个逆变器的可变电容电路构成的振荡器。 每个可变电容电路包括连接在相应逆变器的输出节点和规定电位线之间的多组传输门，熔丝和电容器。

公开(公告)号：US06421286B1

公开(公告)日：2002-07-16

申请号：US09978819

申请日：2001-10-18

申请人： Jun Ohtani ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Tomoya Kawagoe

发明人： Jun Ohtani ,  Tsukasa Ooishi ,  Hideto Hidaka ,  Tomoya Kawagoe

IPC分类号： G11C700

CPC分类号： G11C29/72 ,  G11C29/44

摘要： Built-in self-test circuit and built-in redundancy analysis circuit are provided commonly to plural DRAM cores. Built-in redundancy analysis circuit determines a defective address to be replaced with one of plural spare memory cell rows and plural spare memory cell columns according to an address signal and a detection result of a defective memory cell from built-in self-test circuit. Built-in redundancy analysis circuit controls an effective service area of an address storage circuit into which a defective address is stored according to a capacity of a DRAM core to be tested.

摘要翻译： 内置自检电路和内置冗余分析电路通常提供给多个DRAM内核。 内置冗余分析电路根据地址信号和内置的自检电路中的有缺陷的存储单元的检测结果来确定要被多个备用存储单元行和多个备用存储单元列中的一个替换的缺陷地址。 内置冗余分析电路根据要测试的DRAM内核的容量来控制存储有缺陷地址的地址存储电路的有效服务区域。